Introduction to Micro Controllers & Embedded System Design Interrupt Department of Electrical & Computer Engineering Missouri University of Science & Technology hurson@mst.edu A.R. Hurson

An interrupt is the occurrence of an event out of normal sequence of machine’s operation. It causes a temporary suspension of a program while the event is serviced by another program known as interrupt handlers or interrupt service routine, very similar to a subroutine call. A.R. Hurson

In microcontroller, interrupt allows the system to respond asynchronously to an event and deal with the event. An interrupt driven system gives the illusion of doing many things simultaneously. A.R. Hurson

Main Program Time Main ISR A.R. Hurson

There are five interrupt sources in 8051: Two external, two timers, and a serial port interrupt. Note: it is possible that more than one interrupt happen simultaneously or an interrupt occurs while another interrupt being serviced. A.R. Hurson

Timer CONtrol register: Bit Symbol Address Semantic TCON.7 TF1 8FH Timer1 overflow flag. Set by hardware upon overflow; cleared by software or hardware when processor vectors to interrupt service routine TCON.6 TR1 8EH Timer1 run-control bit. Set/cleared by software to turn timer on/off TCON.5 TF0 8DH Timer0 overflow flag TCON.4 TR0 8CH Timer0 run-control bit A.R. Hurson

Timer CONtrol register: Bit Symbol Address Semantic TCON.3 IE1 8BH TCON.2 IT1 8AH External interrupt1 type flag. Set/cleared by software TCON.1 IE0 89H External interrupt0 flag. TCON.0 IT0 88H External interrupt0 type flag A.R. Hurson

Serial port control register BIT Symbol Address Semantics SCON.7 SM0 9FH Serial port mode bit 0 SCON.6 SM1 9EH Serial port mode bit 1 SCON.5 SM2 9DH Serial port mode bit 2. Enables multiprocessor communications in modes 2 and 3. SCON.4 REN 9CH Receiver enable (must be set to receive) SCON.3 TB8 9BH Transmit bit 8. 9th bit transmitted in modes 2 and 3. Set/cleared by software SCON.2 RB8 9AH Receive bit 8 SCON.1 TI 99H Transmit interrupt flag. Set at the end of character transmission. Cleared by software SCON.0 RI 98H Receive interrupt flag. Set at the end of character reception. Cleared by software A.R. Hurson

Interrupt flag bits INTERRUPT FLAG SFR and bit position External0 IE0 TCON.1 IE1 TCN.3 Timer1 TF1 TCON.7 Timer0 TF0 TCON.5 Serial Port TI SCON.1 RI SCON.0 A.R. Hurson

Enabling and disabling Interrupts Each interrupt source can be individually enabled or disabled through the bit addressable special function register IE (Interrupt Enable) at address 0A8H. Note: There is a global enable/disable bit that can be cleared to disable all interrupts or set to turn on interrupts. A.R. Hurson

Byte address Byte address 90 8D 8C 8B 8A 89 88 87 83 82 81 80 P1 TH1 TL1 TL0 TMOD TCON PCON DPH DDL SP P0 FF F0 E0 D0 B8 B0 A8 A0 99 98 Byte address B ACC PSW IP P3 IE P2 SBUF SCON A.R. Hurson

Interrupt bits BIT Symbol Bit address Semantics 1 = Enable, 0 = Disable IE.7 EA AFH Global enable/disable interrupt IE.6 - AEH Unused IE.5 ET2 ADH Enable timer2 interrupt(8052) IE.4 ES ACH Enable Serial port interrupt IE.3 ET1 ABH Enable timer1 interrupt IE.2 EX1 AAH Enable external1 interrupt IE.1 ET0 A9H Enable timer0 interrupt IE.0 EX0 A8H Enable external0 interrupt A.R. Hurson

Note: Two bits must be set to enable any interrupt: The individual interrupt bit and the global interrupt bit. Question: do the above solutions have exactly the same effect? Example: SETB ET1 ; Enable timer1 interrupt bit SETB EA ; Enable global interrupt bit Alternatively, we can write: MOV IE, #10001000B A.R. Hurson

Interrupt Priority Each interrupt source is individually programmed to one of two priority levels via bit addressable special function register IP (Interrupt Priority) at address 0B8H. A.R. Hurson

1 = Higher level, 0 = Lower level Interrupt priority bits BIT Symbol Bit address Semantics 1 = Higher level, 0 = Lower level IP.7 - Unused IP.6 IP.5 PT2 0BDH Priority for timer2 interrupt(8052) IP.4 PS 0BCH Priority for Serial port interrupt IP.3 PT1 0BBH Priority for timer1 interrupt IP.2 PX1 0BAH Priority for external1 interrupt IP.1 PT0 0B9H Priority for timer0 interrupt IP.0 PX0 0B8H Priority for external0 interrupt A.R. Hurson

Order of handling several interrupts: ISR is interrupted if a higher priority interrupt occurs while servicing a lower priority interrupt. A high-priority interrupt cannot be interrupted. The main program can always be interrupted regardless of the priority of the interrupt. A.R. Hurson

Order of handling several interrupts: If two interrupts of different priorities happen simultaneously, the higher priority interrupt will be serviced first. If two interrupts of the same priority occurs simultaneously, a fixed polling sequence determines which is serviced first, as follows. External0, Timer0, External1, Timer1, Serial Port A.R. Hurson

Processing Interrupts: In case of an interrupt the system follows the following steps: The current instruction completes execution, The content of PC is saved on the stack, The current interrupt status is saved internally, The interrupts are blocked at the level of interrupt, The PC is loaded with the vector address of the ISR, The ISR executes ISR takes action in response to the interrupt ISR finishes with a RETI instruction Execution of main program continues from where it left off. A.R. Hurson

Interrupt vector When an interrupt is accepted the value loaded into the PC is called the interrupt vector which is the address of the start of ISR routine for the interrupting source. When vectoring to an interrupt, the flag that initiated the interrupt is automatically cleared by hardware, except RI and TI flags which trigger the serial port interrupt. A.R. Hurson

Interrupt vector Note: System reserves eight bytes for each interrupt. Flag Vector address System reset RST 0000H External0 IE0 0003H Timer0 TF0 000BH External1 EE1 0013H Timer1 TF1 001BH Serial port RI or TI 0023H A.R. Hurson

Example: ORG 0000H ; Reset entry point LJMP MAIN  ORG 0030H ; Main program entry point MAIN:  A.R. Hurson

Graphical representation FFFF 0000 LJMP MAIN 002F 0030 Main program Reset and Interrupt Entry points A.R. Hurson

Example: Assume we have just one interrupt source (say Timer0) ORG 0000H ; Reset entry point LJMP MAIN ORG 000BH ; Timer0 entry point TOISR:  ; Timer0 ISR begins  RETI ; Return to main program MAIN:  : Main program A.R. Hurson

Example: If an ISR is longer than 8 bytes, then its code must be somewhere else: ORG 0000H ; Reset entry point LJMP MAIN ORG 000BH LJMP TOISR; ORG 0030H MAIN:  : Main program  TOISR:  ; Timer0 ISR begins RETI ; Return to main program A.R. Hurson

Example: Write a program using Timer0 and interrupt to create a 10Khz square wave on P1.0 A.R. Hurson

0030 758902 MAIN: MOV TMOD, #02H ; Timer0, Mode2 0000 ORG 0000H 0000 020030 LJMP MAIN 000B ORG 000BH 000B B290 T0ISR: CPT P1.0 000D 32 RETI A, R5 0030 ORG 0030H 0030 758902 MAIN: MOV TMOD, #02H ; Timer0, Mode2 0033 758CCE MOV TH0, #-50 ; 50 s delay 0036 D28C SETB TR0 ; Start Timer 0038 75A882 MOV IE, #82H ; Enable Timer0 ; interrupt 003B 80FE SJMP $ A.R. Hurson

Serial Port interrupts Serial port interrupts trigger when either the transmit interrupt flag (TI) or the receive interrupt flag (RI) is set. A transmit interrupt occurs when transmission of the previous character written to SBUF has finished. A receive interrupt occurs when a character has been completely received and is waiting in SBUF to be read. Serial port interrupts are slightly different from other types of interrupts in the sense that the serial port interrupt is cleared by software rather than hardware. A.R. Hurson