Winter 2017 S. Areibi School of Engineering University of Guelph ENG3380 Computer Organization and Architecture “Micro Programmed Control Design” Winter 2017 S. Areibi School of Engineering University of Guelph

Topics CPU main Components Types of Control Units History Programmable Control Units Example Recent Developments Summary School of Engineering

References “Computer Organization and Architecture: Designing for Performance”, 10th edition, by William Stalling, Pearson. “Computer Organization and Design: The Hardware/Software Interface”, 4th edition, by D. Patterson and J. Hennessy, Morgan Kaufmann Computer Organization and Architecture: Themes and Variations”, 2014, by Alan Clements, CENGAGE Learning School of Engineering

Introduction

The Central Processing Unit (CPU) The CPU has four main components: The Control Unit (along with the IR) interprets the machine language instruction and issues the control signals to make the CPU execute that instruction. The ALU (Arithmetic Logic Unit) that does the arithmetic and logic. The Register Set (Register File) that stores temporary results related to the computations. There are also Special Purpose Registers used by the Control Unit. An internal bus structure for communication.

A Basic Computer Model

The Control Unit The function of the control unit is to decode the binary machine word in the IR (Instruction Register) and issue appropriate control signals. These cause the computer to execute its program.

Two Options for the Control Unit Hardwired: The control signals are generated as an output of a set of basic logic gates, the input of which derives from the binary bits in the Instruction Register. Microprogrammed: The control signals are generated by a microprogram that is stored in Control Read Only Memory (CROM). The microcontroller fetches a control word from the CROM and places it into the MBR, from which control signals are emitted.

Control Unit Implementation Hardwired Instruction code Combinational Logic Circuits Memory Sequence Counter . Control signals Microprogrammed Control signals Next Address Generator (sequencer) CAR Memory CDR Decoding Circuit . CAR: Control Address Register CDR: Control Data Register Instruction code

Problems With Hard Wired Designs Sequencing & micro-operation logic gets complex Difficult to design, prototype, and test Resultant design is inflexible, and difficult to build upon (Pipeline, multiple computation units, etc.) Adding new instructions requires major design and adds complexity quickly

Micro-programmed Control Use sequences of instructions to control complex operations An alternative to a hardwired control unit Called micro-programming, microcode, or firmware

Tasks Done By Microprogrammed Control Unit Microinstruction sequencing Microinstruction execution Must consider both together

Control Unit Organization A control unit with its binary control values stored as words in memory is called a micro-programmed control. Each word in the control memory contains a microinstruction that specifies one or more micro-operations for the system. A sequence of microinstructions constitutes a microprogram. A microprogram is often fixed at the time of the system design and so is usually stored in ROM. A microprogram can also be written in RAM but has to be loaded initially at system startup. microinstructions microprogram

Control Unit Organization Sequencing Logic Module Generates the address of the next microinstruction Control Logic Module Generates control signals

Next-address generator (sequencer) Control address register Control memory (ROM) Control data register Control word Next-address information External input Sequencer »Determine the address sequence that is read from control memory »Next address of the next microinstruction can be specified several way depending on the sequencer input. Sequencing Capabilities Required in a Control Storage Incrementing of the control address register Unconditional and conditional branches A mapping process from the bits of the machine instruction to an address for control memory A facility for subroutine call and return

Sequencer

A Simple Computer & its Control Unit

Control Signal Sources Clock One micro-instruction (or set of parallel micro-instructions) per clock cycle Instruction Register (IR) Op-code for current instruction Determines which micro-instructions are performed Flags State of CPU Results of previous operations From Control Bus Interrupts / Bus Requests Acknowledgements

Control Signals Outputs Within CPU Cause data movement Activate specific functions Via Main Bus To memory To I/O modules

Control Signals

The Internal Bus ?

Advantages and Disadvantages of Microprogramming Simplifies design of control unit Cheaper Less error-prone Slower than a pure hard-wired implementation RISC processors typically use hardwired control units because of their simpler instruction formats. Bugs and Errata can be corrected by microcode update E.g. Intel Core 2 Duo – bugs and possible security vulnerabilities resolved via microcode update

Advantages and Disadvantages of Microprogramming Instructions can be easily be added with microprogramming compared with hardwired control units. Specifying the architecture and instruction set becomes a software programming issue rather than hardware design problem.

History

Maurice Wilkes Maurice Wilkes worked in the Computing Laboratory at Cambridge University beginning in 1936, but mostly from 1945 as he served in WW 2. On May 6, 1949 the EDSAC was first operational, computing the values of N2 for 1  N  99. In 1951, Wilkes published The Preparation of Programs for Electronic Digital Computers, the first book on programming. Also in 1951, Wilkes published a paper “The Best Way to Design an Automatic Calculating Machine” that described a technique that he called microprogramming. This technique is still in use today and still has the same name.

The 1960’s and 1970’s In the 1960s and 1970s, microprogramming was one of the most important techniques used in implementing machines. Through most of that period, machines were implemented with discrete components or MSI (medium-scale integration—fewer than 1000 gates per chip) The hardwired implementations were faster, but too costly for most machines. Furthermore, it was very difficult to get the control correct, and changing ROMs was easier than replacing a random logic control unit. Eventually, microprogrammed control was implemented in RAM, to allow changes late in the design cycle, and even in the field after a machine shipped.

Side–Effects of Microprogramming It is a simple fact that the introduction of microprogramming allowed the development of Instruction Set Architectures of almost arbitrary complexity. The VAX series, marketed by the Digital Equipment Corporation, is usually seen as the “high water mark” of microprogrammed designs. The later VAX designs supported an Instruction Set Architecture with more than 300 instructions and more than a dozen addressing modes.

Microprogramming and Memory Technologies The drawback of microcode has always been memory performance; the CPU clock cycle is limited by the time to read the memory. In the 1950’s, microprogramming was impractical for two reasons: The memory available was not reliable, and The memory available was the same slow core memory as used in the main memory of the computer.

Microprogramming and Memory Technologies In the late 1960’s, semiconductor memory (SRAM) became available for the control store. It was ten times faster than the DRAM used in main memory. This speed difference that opened the way for microcode. In the late 1970’s, cache memories using the SRAM became popular. At this point, the CROM lost its speed advantage. For these reasons, instruction sets invented since 1985 have not relied on microcode.

Microprogrammed Control

Microprogrammed Control Unit Organization Control Address Register (CAR) specifies the address of the microinstruction. The control data register (CDR) may hold the instruction currently being executed. The next address generator produces the next address. Microprogram sequencer functions: Increment CAR by one Transfer external address into CAR Load initial address into CAR to start control operations CAR CDR

Microprogrammed Control Organization Control data register (CDR)- or pipeline register Holds microinstruction read from control memory Allows execution of microoperations specified by control word simultaneously with generation of next microinstruction Control unit can operate without CDR Control word Next Address Generator (sequencer) CAR Memory (ROM) CDR External input Control word Next Address Generator (sequencer) CAR Memory (ROM) External input

Control Unit Organization A control unit with its binary control values stored as words in memory is called a micro-programmed control. Each word in the control memory contains a microinstruction that specifies one or more micro-operations for the system. A sequence of microinstructions constitutes a microprogram. A microprogram is often fixed at the time of the system design and so is usually stored in ROM. A microprogram can also be written in RAM but has to be loaded initially at system startup. microinstructions microprogram

Control Unit Organization The Control Memory contains sequences of microinstructions that provide the control signals to execute instruction cycles, e.g. Fetch, Indirect, Execute, and Interrupt. Tasks of Control Unit: Microinstruction sequencing Microinstruction execution May be expected to complete instruction execution in “1” clock cycle. How is this possible?

Microinstruction Sequencing Design Considerations: Size of microinstruction Address-generation time Determined by instruction registers Next sequential branch Branch

Micro-program Word Length Based on 3 factors Maximum number of simultaneous micro-operations supported The way control information is represented or encoded The way in which the next micro-instruction address is specified

The Microprogrammed Control Unit

Micro-instruction Types Each micro-instruction specifies single (or few) micro-operations to be performed (vertical micro-programming) Vertical instructions must be decoded to produce control signals. Slower than horizontal microprogramming, but take up less memory (ROM) space. Each micro-instruction specifies many different micro-operations to be performed in parallel (horizontal micro-programming) Requires more memory, but Requires little if any decoding.

Horizontal vs Vertical Microprogramming Horizontal Microprogrammed or Unpacked Hard Direct Vertical Microprogrammed or Packed Soft Indirect

Microinstruction Encoding - Direct Encoding Wide memory word High degree of parallel operations possible Little encoding of control information

Microinstruction Encoding - Indirect Encoding Width is narrow n control signals encoded into log2 n bits Limited ability to express parallelism Considerable encoding of control information requires external memory word decoder to identify the exact control line being manipulated

Horizontal Micro-programming Wide control memory word High degree of parallel operations possible Little encoding of control information Faster

Vertical Micro-programming Width can be much narrower Control signals encoded into function codes – need to be decoded More complex, more complicated to program, less flexibility More difficult to modify Slower

Typical Microinstruction Formats

Example Microprogramming Formats MicroProgram Counter Subroutines Stack Control Register (MicroProgram Format)

Microprogram Routines Group of microinstructions stored in control memory Each computer instruction has its own microprogram routine to generate microoperations that execute the instruction

Conditional Branching Branching from one routine to another depends on status bit conditions Status bits provide parameter info such as Carry-out of adder Sign bit of number Mode bits of instruction Info in status bits can be tested and actions initiated based on their conditions: 1 or 0 Unconditional branch Fix value of status bit to 1

Recall: Micro-sequencing

Example of Control Memory Organization Microinstructions: Generate Control Signals Provide Branching

Mapping of Instruction Each computer instruction has its own microprogram routine stored in a given location of the control memory Mapping Transformation from instruction code bits to address in control memory where routine is located

Mapping of Instruction Example Mapping 4-bit operation code to 7-bit address OP-codes of Instructions ADD AND LDA 0000 0001 0010 Address 0 0000 00 0 0001 00 0 0010 00 Mapping bits 0 xxxx 00 ADD Routine AND Routine LDA Routine Control memory

Address Sequencing Address sequencing capabilities required in control unit Incrementing CAR Unconditional or conditional branch, depending on status bit conditions Mapping from bits of instruction to address for control memory Facility for subroutine call and return

Address Sequencing Instruction code Mapping Multiplexers logic Multiplexers Control memory (ROM) Subroutine Register (SBR) Branch Status bits Microoperations Control Address Register (CAR) Incrementer MUX select select a status bit Branch address

Next Address Decision Depending on ALU flags and control buffer register: Get next instruction Add 1 to control address register Jump to new routine based on jump microinstruction Load address field of control buffer register into control address register Jump to machine instruction routine Load control address register based on opcode in IR

Microprogrammed Control Unit

Design Considerations Necessity of speed Size of Microinstructions Address generation Branches Both conditional and unconditional Based on current microinstruction, condition flags, contents of IR Based on format of address information Two address fields Single address field Variable format

Branch Control: Two Address Fields Branch based upon: Instruction Opcode Address 1 Address 2 Does require a wide microinstruction, but no address calculation is needed

Branch Control: Single Address Field Branch based upon: Next instruction Address Opcode Does require more circuitry, e.g. adder

Branch Control: Variable Format One bit determines microinstruction format: Control signal format Branch format Does require even more circuitry, and is slowest.

Example #1

Microprogram Example Computer Configuration MUX 10 AR Address Memory PC Address Memory 2048 x 16 DR 15 Arithmetic logic and shift unit AC SBR 6 CAR Control memory 128 x 20 Control unit Computer Configuration

Microprogram Example Computer instruction format Microinstruction Format EA is the effective address Symbol OP-code Description ADD 0000 AC AC + M[EA] BRANCH 0001 if (AC < 0) then (PC  EA) STORE 0010 M[EA]  AC EXCHANGE 0011 AC  M[EA], M[EA]  AC Computer instruction format I Opcode 15 14 11 10 Address Four computer instructions F1 F2 F3 CD BR AD 3 2 7 F1, F2, F3: Microoperation fields CD: Condition for branching BR: Branch field AD: Address field

Microinstruction Fields F1 Microoperation Symbol 000 None NOP 001 AC  AC + DR ADD 010 AC  0 CLRAC 011 AC  AC + 1 INCAC 100 AC  DR DRTAC 101 AR  DR(0-10) DRTAR 110 AR  PC PCTAR 111 M[AR]  DR WRITE F2 Microoperation Symbol 000 None NOP 001 AC  AC - DR SUB 010 AC  AC  DR OR 011 AC  AC  DR AND 100 DR  M[AR] READ 101 DR  AC ACTDR 110 DR  DR + 1 INCDR 111 DR(0-10)  PC PCTDR F3 Microoperation Symbol 000 None NOP 001 AC  AC  DR XOR 010 AC  AC’ COM 011 AC  shl AC SHL 100 AC  shr AC SHR 101 PC  PC + 1 INCPC 110 PC  AR ARTPC 111 Reserved

Microinstruction Fields CD Condition Symbol Comments 00 Always = 1 U Unconditional branch 01 DR(15) I Indirect address bit 10 AC(15) S Sign bit of AC 11 AC = 0 Z Zero value in AC BR Symbol Function 00 JMP CAR  AD if condition = 1 CAR  CAR + 1 if condition = 0 01 CALL CAR  AD, SBR  CAR + 1 if condition = 1 CAR  CAR + 1 if condition = 0 10 RET CAR  SBR (Return from subroutine) 11 MAP CAR(2-5)  DR(11-14), CAR(0,1,6)  0

Symbolic Microinstruction Sample Format Label: Micro-ops CD BR AD Label may be empty or may specify symbolic address terminated with colon Micro-ops consists of 1, 2, or 3 symbols separated by commas CD one of {U, I, S, Z} U: Unconditional Branch I: Indirect address bit S: Sign of AC Z: Zero value in AC BR one of {JMP, CALL, RET, MAP} AD one of {Symbolic address, NEXT, empty}

Fetch Routine Fetch routine - Read instruction from memory - Decode instruction and update PC AR  PC DR  M[AR], PC  PC + 1 AR  DR(0-10), CAR(2-5)  DR(11-14), CAR(0,1,6)  0 Symbolic microprogram for fetch routine: ORG 64 PCTAR U JMP NEXT READ, INCPC U JMP NEXT DRTAR U MAP FETCH: Binary microporgram for fetch routine: 1000000 110 000 000 00 00 1000001 1000001 000 100 101 00 00 1000010 1000010 101 000 000 00 11 0000000 Binary address F1 F2 F3 CD BR AD Microinstructions for fetch routine:

Symbolic Microprogram Control memory: 128 20-bit words First 64 words: Routines for 16 machine instructions Last 64 words: Used for other purpose (e.g., fetch routine and other subroutines) Mapping: OP-code XXXX into 0XXXX00, first address for 16 routines are 0(0 0000 00), 4(0 0001 00), 8, 12, 16, 20, ..., 60 ORG 0 NOP READ ADD ORG 4 ARTPC ORG 8 ACTDR WRITE ORG 12 ACTDR, DRTAC ORG 64 PCTAR READ, INCPC DRTAR I U S CALL JMP MAP RET INDRCT NEXT FETCH OVER ADD: BRANCH: OVER: STORE: EXCHANGE: FETCH: INDRCT: Label Microops CD BR AD Partial Symbolic Microprogram

Binary Microprogram Address Binary Microinstruction Micro Routine Decimal Binary F1 F2 F3 CD BR AD ADD 0 0000000 000 000 000 01 01 1000011 1 0000001 000 100 000 00 00 0000010 2 0000010 001 000 000 00 00 1000000 3 0000011 000 000 000 00 00 1000000 BRANCH 4 0000100 000 000 000 10 00 0000110 5 0000101 000 000 000 00 00 1000000 6 0000110 000 000 000 01 01 1000011 7 0000111 000 000 110 00 00 1000000 STORE 8 0001000 000 000 000 01 01 1000011 9 0001001 000 101 000 00 00 0001010 10 0001010 111 000 000 00 00 1000000 11 0001011 000 000 000 00 00 1000000 EXCHANGE 12 0001100 000 000 000 01 01 1000011 13 0001101 001 000 000 00 00 0001110 14 0001110 100 101 000 00 00 0001111 15 0001111 111 000 000 00 00 1000000 FETCH 64 1000000 110 000 000 00 00 1000001 65 1000001 000 100 101 00 00 1000010 66 1000010 101 000 000 00 11 0000000 INDRCT 67 1000011 000 100 000 00 00 1000100 68 1000100 101 000 000 00 10 0000000

Design of Control Unit microoperation fields 3 x 8 decoder 7 6 5 4 3 2 1 F1 F2 F3 Arithmetic logic and shift unit AND ADD DRTAC AC Load From PC DR(0-10) Select Multiplexers AR Clock DR DRTAR PCTAR

Microprogram Sequencer External (MAP) L I0 3 2 1 Input Load I1 S1 logic MUX1 SBR T S0 Incrementer 1 I Test MUX2 S Z Select Clock CAR Control memory Microops CD BR AD . . . . . .

Input Logic for Microprogram Sequencer MUX2 Select 1 I S Z Test CD Field of CS From CPU BR field of CS L(load SBR with PC) for subroutine Call S0 S1 for next address selection I1I0T Meaning Source of Address S1S0 L 000 In-Line CAR+1 00 0 001 JMP CS(AD) 01 0 010 In-Line CAR+1 00 0 011 CALL CS(AD) and SBR <- CAR+1 01 1 10x RET SBR 10 0 11x MAP DR(11-14) 11 0 L S1 = I1 S0 = I0I1 + I1’T L = I1’I0T Input Logic

Example #2

A Very Simple Computer We shall use some material from a simple computer designed to illustrate various control unit designs. In this design, instruction execution is divided into three phases. Fetch Decode Execute We focus on the first of these phases: fetch, which fetches the next instruction and updates the PC.

The Common Fetch Sequence In the X2 design, the Fetch sequence is divided into four phases, each having duration of one clock pulse. Here are the microoperations associated with the first three phases of the fetch sequence. Step 1: (PC)  MAR, READ. Step 2: (PC) + 4  PC. Step 3: (MBR)  IR.

Control Signals are More Primitive Control signals directly enable transfers, so they must be very low level. Note that the inputs (Fetch, T0, T1, T2) are discrete binary signals. Fetch, T0: (PC)  B1, tra1, B3  MAR, READ. Fetch, T1: (PC)  B1, 4  B2, add, B3  PC. Fetch, T2: (MBR)  B2, tra2, B3  IR.

The X2 Control Signals PC  B1 Copy the contents of the PC onto bus B1 +4  B2 Copy the constant +4 onto B2. MBR  B2 Copy the contents of the MBR onto B2 tra1 Causes the ALU to copy the contents of B1 onto B3 tra2 Causes the ALU to copy the contents of B2 onto B3 add Causes the ALU to add the contents of B1 and B2, placing the sum onto B3. read Causes the memory to be read; place the results in MBR Bus3  MAR Copy the contents of B3 to the MAR Bus3  PC Copy the contents of B3 to the PC Bus3  IR Copy the contents of B3 to the IR

Hardwired Signal Generation The first phase of the fetch sequence has Fetch = 1 T0 = 1. If Fetch = 1 and T0 = 1 then tra1 = 1 (it is asserted) B3  MAR = 1 read = 1 PC  B1 = 1

Microprogrammed Signals   PC  Bus1 +1  Bus2 MBR  Bus2 Bus3  MAR Bus3  PC Bus3  IR add tra1 tra2 read T0 1 T1 T2 The microprogram can be written as 10 0100 0101 0x245 11 0010 1000 0x328 00 1001 0010 0x092

Microprogramming Example Consider the micro–memory associated with bus B1. At address 105 we have MAR  B1. At address 106 we have R  B1.

Horizontal and Vertical Microcode Consider a bus, B1, that can be fed by seven different signal sources. In horizontal microcode, each signal has a bit in the micro-memory. The B1 field would have 8 bits. In vertical microcode, the field would have a binary encoding to indicate the single source to be placed on the bus; here 3 bits.

Advantages of Vertical Microcode One advantage is that it allows a “narrower micro–memory”, fewer bits per word in the micro–memory. But memory is cheap. The major advantage is that it prevents the assertion of two or more data sources on a given bus or two or more simultaneous ALU operations.

B1 With Vertical Microcode

Typical Microinstruction Format Each microinstruction includes the address of the instruction to be executed next. Here is a format that supports a branch. There are two 8-bit addresses. The signal S2 will indicate whether or not the branch is taken. Non-branching instructions have the same value in both fields.

Why Store Addresses in the Microcode Here are two options for a sequence of control signals, taken out of context. The first uses a conditional branch. 0x02C IR  B1, R  B2, add, B3  MAR 0x02D If D = 0 Go To 0x030 0x02E READ Similar code in the modern style 0x02C IR  B1, R  B2, add, B3  MAR, 0x030, 0x02E

Recent Developments

Microprogramming: The Late Evolution Events that lead to the reduced emphasis on microprogramming include: The availability of VLSI technology, which allowed a number of improvements, including on–chip cache memory, at reasonable cost. The availability of ASIC (Application Specific Integrated Circuits) and FPGA (Field Programmable Gate Arrays), each of which could be used to create custom circuits that were easily tested and reconfigured. The beginning of the RISC (Reduced Instruction Set Computer) movement, with its realization that complex instruction sets were not required.

What Happened to Microcode? Control units for RISC designs tend not to use microprogramming, but the simpler and faster hardwired designs: One reason is that the simplicity of the control unit does not require microprogramming. Another possible reason is that the speed of a modern pipelined control unit requires control signals to be issued at a rate faster than SRAM read-only memory can deliver them.

Advantages and Disadvantages of Microprogramming Simplifies design of control unit Cheaper to design Less error-prone Much easier to modify Supports having multiple versions / models Disadvantage: Slower More expensive to produce in quantities

Summary

Summary Microprogramming – alternative to hard-wired control units, provides more flexibility in designing the processor and control unit. Disadvantages – not as fast as a hard-wired implementation, RISC processors typically use hardwired control units. Microprogramming allows for errors microcode to be corrected via patches (with writable memory i.e. EEPROM) (as in C2D) Horizontal microcode represents each control signal as a bit with little or no encoding used. Vertical microcode encodes mutually exclusive control signals in different fields, which must then be decoded to produce the control signals. (Which requires more time because of additional combinational circuits).

Interesting Facts The Nintendo 64’s graphics and audio co-processor (MIPS 4000 based) utilized programmable microcode Allowed for tuning of the processor for extra speed and quality e.g. to run at 640x480. Playstation 2’s vector processor units were microprogrammable via microcode. 3D Geometry and floating point arithmetic Microcode allows for programmers to fine-tune the processors at a below assembly code level, allows for more optimization.

References http://fourier.eng.hmc.edu/e85/lectures/processor/node11.html http://www.cs.binghamton.edu/~reckert/hardwire3new.html http://en.wikipedia.org/wiki/Microcode http://en.wikipedia.org/wiki/Hardwired_control http://en.wikipedia.org/wiki/Control_unit http://en.wikipedia.org/wiki/Core_2_duo

End Slides

Review Questions What is the difference between horizontal and vertical microinstructions? Why is micro programmed control used instead of hardwired control for the control unit. What are the advantages and disadvantages of micro programmed control compared with a hardwired control unit implementation? What are the main tasks performed by a micro programmed control unit?

Review Questions Why are vertical microinstructions slower than horizontal microinstructions? What is the preferred sequencing technique? What are the differences between explicit techniques and implicit techniques? What range of values does the length of vertical and horizontal microinstructions fall under? What does the control memory contain? What concerns are involved in the design of a microinstruction sequencing technique?