ECE 3430 – Intro to Microcomputer Systems ECE 3430 – Introduction to Microcomputer Systems University of Colorado at Colorado Springs Lecture #14 Agenda Today Interrupts (a final say) Clock System Computer-Operating-Properly Watchdog Real-Time Clock Module MSP432 Timer_A Module Timer_A Example: Timer Overflow Interrupt Lecture #14 ECE 3430 – Intro to Microcomputer Systems Fall 2015

Interrupts (A Final Say) Interrupt Overhead (Latency) Interrupts take a fixed number of clock cycles to initialize and get ready to execute the ISR. It takes several cycles to load up the stack before entering the ISR. It takes several cycles to unload the stack after leaving an ISR. [ The ARM processor uses interrupt “tail-chaining” to avoid the stack unload/load overhead when processing back-to-back interrupts. This helps mitigate the latency in some situations. ] - The CPU may be in a low-power mode and require “wake-up” time. The overhead should be measured to determine if an interrupt should be used in the first place. If the latency and frequency are both high, polling is typically a better solution! Lecture #14 ECE 3430 – Intro to Microcomputer Systems Fall 2015

ECE 3430 – Intro to Microcomputer Systems MSP432 Clock System Multiple Clock Domains for CPU and Peripherals Multiple clock domains are provided because perhaps the CPU doesn’t need to run as fast as the peripherals—or vice versa. Clocking faster than necessary wastes power without end-user benefit!  Should run CPU and peripherals no faster than necessary to give desired functionality. Some clock domains in MSP432: Master Clock (MCLK)  CPU is driven by this Sub-System Master Clock (SMCLK) Auxiliary Clock (ACLK) Others… Different peripherals may use different clock domains. Each of the clock domains above can be sourced by different oscillator sources (see datasheet). Each of the clock domains can also be divided down by a factor of 1, 2, 4, or 8. Lecture #14 ECE 3430 – Intro to Microcomputer Systems Fall 2015

ECE 3430 – Intro to Microcomputer Systems MSP432 Clock System The CPU (MCLK) is driven by a built-in digitally controlled oscillator (DCO) by default. The sub-system master clock (SMCLK) is also driven by DCO by default. ACLK comes from a low-frequency, external oscillator if present. Some clock signals can be brought out of the uC through port pins (configured as outputs) for use by external devices. External crystals can be more accurate than an RC-based internal oscillator—but usually this additional accuracy is not required. Lecture #14 ECE 3430 – Intro to Microcomputer Systems Fall 2015

ECE 3430 – Intro to Microcomputer Systems MSP432 Clock System Do clock accuracy and stability matter? Accuracy: How close the frequency is to the advertised. Stability: How much or little the frequency shifts with time and temperature. How long will your system run without a reset? Is precise timing needed? Are you keeping track of “real time”? What range of temperatures will your system be operating in? … Lecture #14 ECE 3430 – Intro to Microcomputer Systems Fall 2015

ECE 3430 – Intro to Microcomputer Systems MSP432 Clock System Oscillator Faults Having multiple oscillator candidates for a clock source allows for some fault tolerance! What happens if an external crystal oscillator fails and your system is part of a satellite in space?  Software can switch over to an alternate, less-desirable or backup oscillator as a fail-safe! Lecture #14 ECE 3430 – Intro to Microcomputer Systems Fall 2015

Detecting Oscillator Faults An RC circuit can be used as a primitive way of detecting an oscillator fault. (The MSP432 likely uses a more sophisticated hardware technique) Remember:  = RC Vout = Vin · e-(t/) Volts (V) Time (t) Lecture #14 ECE 3430 – Intro to Microcomputer Systems Fall 2015

ECE 3430 – Intro to Microcomputer Systems Watchdog Timer MSP432 Watchdog Must be periodically reset by software to keep the timer from expiring and resetting the system. Virtually all uC systems have Watchdog timers. The details of how to do a “software check-in” vary from one system to another. In the MSP432, the WDTCNTCL bit in the WDTCTL register must be written as a 1 before the timer expires. The upper 8 bits must be 0x5A (WDTPW). In the MSP432, setting the WDTHOLD bit in the WDTCTL register suspends the Watchdog timer. MSP432 Watchdog can be clocked from SMCLK or ACLK. Clock source can be scaled down before entering the counter. Lecture #14 ECE 3430 – Intro to Microcomputer Systems Fall 2015

ECE 3430 – Intro to Microcomputer Systems Watchdog Timer MSP432 Watchdog In the MSP432, can alternatively be configured as an interval timer. Set the WDTTMSEL bit in the WDTCTL to configure it as a timer. When it expires, no reset occurs and the usual reset vector is not acknowledged. An alternate vector is consulted when the timer overflows (if and only if the maskable interrupts are enabled). Using interrupts or not, a flag is raised. If using interrupts, the hardware will automatically clear this flag (to save software the trouble). If no interrupts, software must poll and clear this flag manually. Lecture #14 ECE 3430 – Intro to Microcomputer Systems Fall 2015

ECE 3430 – Intro to Microcomputer Systems MSP432 Real-Time Clock Real-Time Clock A Real-Time Clock (RTC) module is present to provide real measurement of time. Keeping track of “wall time” can be such a common thing to do, the hardware designers provided a hardware module to do it for you. Other uCs might require software keep track of the time based on hardware-generated interrupts. The RTC module can generate an interrupt as an “alarm clock” function. Lecture #14 ECE 3430 – Intro to Microcomputer Systems Fall 2015

ECE 3430 – Intro to Microcomputer Systems MSP432 Timer_A Module We want separate timing circuitry that will run independent of our program. This ensures more precise timing. Our program run times can be unpredictable due to interrupts! For example, a DELAY subroutine or loop may take longer to complete if it is interrupted by an interrupt. Virtually all microcontrollers have timer facilities. The specific details of how that timer works will vary somewhat depending on the design. The MSP432 Timer_A module is very flexible and can be used as: 1) Plain 16-bit Counter (TAR) 2) Input Capture (Timing reception of inputs) 3) Output Compare (Generating precisely-timed outputs) 4) Real Time Interrupts (Generating a periodic interrupt) 5) Pulse Accumulator (Input pulse timer or event counter) 6) … Lecture #14 ECE 3430 – Intro to Microcomputer Systems Fall 2015

Timer Block in Timer_A Module Main Timer_A Register (TAR) / Timer Overflow Interrupt - A 16-bit counter clocked by a ACLK, SMCLK or an external clock. - Has pre-scalar to slow count down. - When overflow occurs (0xFFFF  0x0000), an interrupt can be triggered. - On POR, the counter is cleared to 0x0000. - This counter is readable and writable by software. - When overflow occurs, the timer A interrupt flag (TAIFG) is set in TACTL register. - If configured to generate an interrupt, the ISR is called. - The ISR may need to clear the TAIFG if it is not cleared automatically. - The timer overflow interrupt is maskable, so you must: Ensure the I flag in the PRIMASK CPU register is clear (global enable). Ensure the NVIC is configured to allow the interrupt. Ensure the TAIE flag in the TACTL register is set (local enable). Pre-Scalar divide by 1, 2, 4, or 8 Main Timer (TAR) 16-bit Configurable Clock Source    TAIFG TAR High TAR Low Lecture #14 ECE 3430 – Intro to Microcomputer Systems Fall 2015

Timer Block in Timer_A Module Main Timer_A Register (TAR) / Timer Overflow Interrupt - The “Timer_A clock source select” bits are located in TACTL (TASSELx). Bit 9 Bit 8 Source 0 0 TACLK (external) 0 1 ACLK (internal) 1 0 SMCLK (internal) 1 1 INCLK (external) - The “Timer_A input divider” bits are located in TACTL (IDx). Bit 7 Bit 6 Pre-Scalar 0 0 1 (fastest overflow rate) 0 1 2 1 0 4 1 1 8 (slowest overflow rate) Lecture #14 ECE 3430 – Intro to Microcomputer Systems Fall 2015

Timer Block in Timer_A Module Main Timer_A Register (TAR) / Timer Overflow Interrupt - The “Timer_A mode control” bits are located in TACTL (MCx). Bit 5 Bit 4 Mode 0 0 Stop mode (timer is halted, power is conserved) 0 1 Up mode (timer counts up to TACCR0) 1 0 Continuous mode (timer counts up to 0xFFFF) 1 1 Up/down mode (timer counts up to TACCR0 and then down to 0) - Bit 3 of TACTL is unused. - Bits 15-10 of TACTL are unused. - The “Timer_A clear” bit is located in TACTL (TACLR), bit 2. Setting it resets TAR, the clock divider, and the count direction. - The “Timer_A interrupt enable” is located in TACTL (TAIE), bit 1. Setting it “locally” enables interrupts. - The “Timer_A interrupt flag” is located in TACTL (TAIFG), bit 0. It is set by hardware and should be cleared by software (if necessary). Lecture #14 ECE 3430 – Intro to Microcomputer Systems Fall 2015

Timer Block in Timer_A Module Main Timer_A Register (TAR) / Timer Overflow Interrupt Example) Use TAR to pulse P1.4 every 262 ms. Assume 1 MHz SMCLK. 1 MHz/4 = 250 kHz 4 us/count * 65536 counts ~= 262 ms. Startup LDR R0, =P1DIR ; make P1.4 an output, all others inputs MOV R1, #0x10 STRB R1, [R0] LDR R0, =TACTL ; set source, divider, and mode MOV R1, #TASSEL_2+ID_2+MC_2 STRH R1, [R0] ORR R1, #TAIE ; tell timer to generate interrupts STRH R1, [R0] LDR R0, =NVIC_ISER0 ; tell NVIC to pass on the interrupts to the CPU MOV R1, 0x200 ; allow IRQ 9 STR R1, [R0] CPSIE I ; tell CPU to allow maskable interrupts globally Done B Done Lecture #14 ECE 3430 – Intro to Microcomputer Systems Fall 2015

Timer Block in Timer_A Module Main Timer_A Register (TAR) / Timer Overflow Interrupt ; ISR for timer overflow interrupt. ; Pulse P1.4 (1 -> 0) and clear the TAIFG flag. ; Hardware automatically preserved R0 and R1—so I don’t have to. TA0_N_IRQHandler LDR R0, =P1OUT ; load P1OUT address LDRB R1, [R0] ; sample P1OUT ORR R1, #0x10 ; force P1.4 high in register STRB R1, [R0] ; force P1.4 high on output BIC R1, #0x10 ; force P1.4 low in register STRB R1, [R0] ; force P1.4 low on output LDR R0, =TACTL ; load TACTL address LDRH R1, [R0] ; sample TACTL BIC R1, #TAIFG ; clear TAIFG flag in register STRH R1, [R0] ; clear TAIFG flag in hardware BX LR ; return from ISR 262 ms ISR P1.4 How accurate would you expect this waveform to be? Lecture #14 ECE 3430 – Intro to Microcomputer Systems Fall 2015