ECE 4110–5110 Digital System Design

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Presentation transcript:

ECE 4110–5110 Digital System Design Lecture #10 Agenda Decoders using Structural VHDL Announcements HW #5 next Lecture #11 Page 1

Decoders using Structural VHDL Binary Decoders (or simply Decoders) - a binary decoder has n inputs and 2n outputs, where - one output is asserted for a given input combination ex) truth table of decoder Input Output 00 0001 01 0010 10 0100 11 1000 - these are key circuits for Address Decoders Other Decoders? (Display decoder, custom decoder, etc..) Lecture #10 Page 2

Decoders using Structural VHDL Decoder Example - Let's design a 2-to-4 Decoder using Structural VHDL - We know we need to describe the following structure: - The output stage of a decoder can be constructed using AND gates - Inverters are needed to give the appropriate code to each AND gate We know what we'll need: 2n AND gates = 4 AND gates n Inverters = 2 Inverters Showing more inverters than necessary to illustrate concept Lecture #11 Page 3

Decoders using Structural VHDL Decoders with ENABLES - An Enable line can be fed into the AND gate - The AND gate now needs (n+1) inputs - Using positive logic: EN = 0, Output = 0 EN =1, Output depends on input code EN ? Lecture #10 Page 4

Decoders using Structural VHDL Decoder Example (without EN) - Let's design the inverter using concurrent signal assignments…. entity inv is port (In1 : in STD_LOGIC; Out1 : out STD_LOGIC); end entity inv; architecture inv_arch of inv is begin Out1 <= not In1; end architecture inv_arch; Lecture #11 Page 5

Decoders using Structural VHDL Decoder Example - Let's design the AND gate using concurrent signal assignments…. entity and2 is port (In1,In2 : in STD_LOGIC; Out1 : out STD_LOGIC); end entity and2; architecture and2_arch of and2 is begin Out1 <= In1 and In2; end architecture and2_arch; Lecture #11 Page 6

Decoders using Structural VHDL Decoder Example - Now let's work on the top level design entity called "decoder_2to4" entity decoder_2to4 is port (A,B : in STD_LOGIC; Y0,Y1,Y2,Y3 : out STD_LOGIC); end entity decoder_2to4; Lecture #11 Page 7

Decoders using Structural VHDL Decoder Example - Now let's work on the top level design architecture called "decoder_2to4_arch" architecture decoder_2to4 _arch of decoder_2to4 is signal A_n, B_n : STD_LOGIC; component inv port (In1 : in STD_LOGIC; Out1 : out STD_LOGIC); end component; component and2 port (In1,In2 : in STD_LOGIC; Out1 : out STD_LOGIC); end component; begin ……… Lecture #11 Page 8

Decoders using Structural VHDL Decoder Example - cont…. begin U1 : inv port map (A, A_n); U2 : inv port map (B, B_n); U3 : and2 port map (A_n, B_n, Y0); U4 : and2 port map (A, B_n, Y1); U5 : and2 port map (A_n, B, Y2); U6 : and2 port map (A, B, Y3); end architecture decoder_2to4 _arch; Lecture #11 Page 9