Presentation is loading. Please wait.

Presentation is loading. Please wait.

Lecture #9 Page 1 Lecture #9 Agenda 1.VHDL : Structural Design Announcements 1.n/a ECE 4110– Digital Logic Design.

Published byLee Sanders Modified over 8 years ago

Similar presentations

Presentation on theme: "Lecture #9 Page 1 Lecture #9 Agenda 1.VHDL : Structural Design Announcements 1.n/a ECE 4110– Digital Logic Design."— Presentation transcript:

1 Lecture #9 Page 1 Lecture #9 Agenda 1.VHDL : Structural Design Announcements 1.n/a ECE 4110– Digital Logic Design

2 Lecture #9 Page 2 Structural Design Structural Design - we can specify functionality in an architecture in two ways 1) Structurally : text based schematic, manual instantiation of another system 2) Behaviorally : abstract description of functionality - we will start with learning Structural VHDL design Components - blocks that already exist and are included into a higher level design - we need to know the entity declaration of the system we are calling - we "declare" a component using the keyword "component" - we declare the component in the architecture which indicates we wish to use it

3 Lecture #9 Page 3 Structural Design Component Syntax component component-name port (signal-name : mode signal-type; signal-name : mode signal-type); -- exactly the same as the Entity declaration without the keyword is end component; Let's build this…

4 Lecture #9 Page 4 Structural Design Component Example - let's use these pre-existing entities "xor2" & "or2" entity xor2 is port (In1, In2 : inSTD_LOGIC; Out1 : outSTD_LOGIC); end entity xor2; entity or2 is port (In1, In2 : inSTD_LOGIC; Out1 : outSTD_LOGIC); end entity or2;

5 Lecture #9 Page 5 Structural Design Component Example - now let's include the pre-existing entities "xor2" & "or2" into our "TOP" design entity TOP is port (A,B,C : inSTD_LOGIC; X : outSTD_LOGIC); end entity TOP; architecture TOP_arch of TOP is component xor2 -- declaration of xor2 component port (In1, In2 : inSTD_LOGIC; Out1 : outSTD_LOGIC); end component; component or2 -- declaration of or2 component port (In1, In2 : inSTD_LOGIC; Out1 : outSTD_LOGIC); end component; begin …..

6 Lecture #9 Page 6 Structural Design Signals - now we want to connect items within an architecture, we need "signals" to do this - we defined signals within an architecture Internal "Signal" Internal "Components"

7 Lecture #9 Page 7 Structural Design Signal Syntax architecture TOP_arch of TOP is signal signal-name : signal-type; signal signal-name : signal-type;

8 Lecture #9 Page 8 Structural Design Let's put the signal declaration into our Architecture - now let's include the pre-existing entities "xor2" & "or2" into our "TOP" design architecture TOP_arch of TOP is signal node1 :STD_LOGIC; component xor2 -- declaration of xor2 component port (In1, In2 : inSTD_LOGIC; Out1 : outSTD_LOGIC); end component; component or2 -- declaration of or2 component port (In1, In2 : inSTD_LOGIC; Out1 : outSTD_LOGIC); end component; begin ….. end architecture TOP_arch; node1

9 Lecture #9 Page 9 Structural Design Component Instantiation - after the "begin" keyword, we can start adding components and connecting signals - we add components with a "Component Instantiation" syntax: label : component-name port map (port => signal, ……) ; NOTE: - "label" is a unique reference designator for that component (U1, INV1, UUT1) - "component-name" is the exact name as declared prior to the "begin" keyword - "port map" is a keyword - the signals with in the ( ) of the port map define how signals are connected to the ports of the instantiated component

10 Lecture #9 Page 10 Structural Design Port Maps - There are two ways describe the "port map" of a component 1) Positional 2) Explicit Positional Port Map - signals to be connected to the component are listed in the exact order as the components port order ex) U1 : xor2 port map (A, B, node1); Explicit Port Map - signals to be connected to the component are explicitly linked to the port names of the component using the "=>" notation (Port => Signal, Port => Signal, ….) ex) U1 : xor2 port map (In1 => A, In2 => B, Out1 => node1);

11 Lecture #9 Page 11 Structural Design Execution - All components are executed CONCURRENTLY - this mimics real hardware - this is different from traditional program execution (i.e., C/C++) which is executed sequentially because We are NOT writing code, we are describing hardware!!!

12 Lecture #9 Page 12 Structural Design Let's put everything together architecture TOP_arch of TOP is signal node1 :STD_LOGIC; component xor2 -- declaration of xor2 component port (In1, In2 : inSTD_LOGIC; Out1 : outSTD_LOGIC); end component; component or2 -- declaration of or2 component port (In1, In2 : inSTD_LOGIC; Out1 : outSTD_LOGIC); end component; begin U1 : xor2port map (In1=>A, In2=>B, Out1=>node1); U2 : or2 port map (In1=>C, In2=>node1, Out1=>X); end architecture TOP_arch; node1 U1 U2

13 Lecture #9 Page 13 Structural Design Generate Statement - there are times when we want to instantiate a large number of the same component (ex. on a bus) - VHDL has a "generate" statement that allows us to instantiate using a loop structure syntax: label : for identifier in range generate component instantiation end generate;

14 Lecture #9 Page 14 Structural Design Generate Statement ex) instantiate 8 inverters assuming X and Y are busses of equal width begin Gen1 : for i in 1 to 8 generate U1 : INV1 port map ( In1=>X(i), In2=>Y(i) ); end generate;

Download ppt "Lecture #9 Page 1 Lecture #9 Agenda 1.VHDL : Structural Design Announcements 1.n/a ECE 4110– Digital Logic Design."

Similar presentations

HDL Programming Fundamentals

HDL Programming Fundamentals
Simulation executable (simv)

Simulation executable (simv)
1 Introduction to VHDL (Continued) EE19D. 2 Basic elements of a VHDL Model Package Declaration ENTITY (interface description) ARCHITECTURE (functionality)

1 Introduction to VHDL (Continued) EE19D. 2 Basic elements of a VHDL Model Package Declaration ENTITY (interface description) ARCHITECTURE (functionality)
ECE C03 Lecture 131 Lecture 13 VHDL Structural Modeling Hai Zhou ECE 303 Advanced Digital Design Spring 2002.

ECE C03 Lecture 131 Lecture 13 VHDL Structural Modeling Hai Zhou ECE 303 Advanced Digital Design Spring 2002.
1 Lecture 13 VHDL 3/16/09. 2 VHDL VHDL is a hardware description language. The behavior of a digital system can be described (specified) by writing a.

1 Lecture 13 VHDL 3/16/09. 2 VHDL VHDL is a hardware description language. The behavior of a digital system can be described (specified) by writing a.
EE 261 – Introduction to Logic Circuits Module #5 Page 1 EE 261 – Introduction to Logic Circuits Module #5 - VHDL Topics A.Hardware Description Languages.

EE 261 – Introduction to Logic Circuits Module #5 Page 1 EE 261 – Introduction to Logic Circuits Module #5 - VHDL Topics A.Hardware Description Languages.
Introduction to VHDL (Lecture #5) ECE 331 – Digital System Design The slides included herein were taken from the materials accompanying Fundamentals of.

Introduction to VHDL (Lecture #5) ECE 331 – Digital System Design The slides included herein were taken from the materials accompanying Fundamentals of.
Lab Lecture 3 VHDL Architecture styles and Test Bench -Aahlad.

Lab Lecture 3 VHDL Architecture styles and Test Bench -Aahlad.
02/02/20091 Logic devices can be classified into two broad categories Fixed Programmable Programmable Logic Device Introduction Lecture Notes – Lab 2.

02/02/20091 Logic devices can be classified into two broad categories Fixed Programmable Programmable Logic Device Introduction Lecture Notes – Lab 2.
Dr. Turki F. Al-Somani VHDL synthesis and simulation – Part 2 Microcomputer Systems Design (Embedded Systems)

Dr. Turki F. Al-Somani VHDL synthesis and simulation – Part 2 Microcomputer Systems Design (Embedded Systems)
VHDL Intro What does VHDL stand for? VHSIC Hardware Description Language VHSIC = Very High Speed Integrated Circuit Developed in 1982 by Govt. to standardize.

VHDL Intro What does VHDL stand for? VHSIC Hardware Description Language VHSIC = Very High Speed Integrated Circuit Developed in 1982 by Govt. to standardize.
1/31/20081 Logic devices can be classified into two broad categories Fixed Programmable Programmable Logic Device Introduction Lecture Notes – Lab 2.

1/31/20081 Logic devices can be classified into two broad categories Fixed Programmable Programmable Logic Device Introduction Lecture Notes – Lab 2.
Kazi Fall 2006 EEGN 4941 EEGN-494 HDL Design Principles for VLSI/FPGAs Khurram Kazi Some of the slides were taken from K Gaj’s lecture slides from GMU’s.

Kazi Fall 2006 EEGN 4941 EEGN-494 HDL Design Principles for VLSI/FPGAs Khurram Kazi Some of the slides were taken from K Gaj’s lecture slides from GMU’s.
Kazi Fall 2006 EEGN 4941 EEGN-494 HDL Design Principles for VLSI/FPGAs Khurram Kazi Some of the slides were taken from K Gaj’s lecture slides from GMU’s.

Kazi Fall 2006 EEGN 4941 EEGN-494 HDL Design Principles for VLSI/FPGAs Khurram Kazi Some of the slides were taken from K Gaj’s lecture slides from GMU’s.
N Structural Modeling: n Entities n Ports n Architectures n Packages.

N Structural Modeling: n Entities n Ports n Architectures n Packages.
ECE 331 – Digital System Design Course Introduction and VHDL Fundamentals (Lecture #1)

ECE 331 – Digital System Design Course Introduction and VHDL Fundamentals (Lecture #1)
VHDL. What is VHDL? VHDL: VHSIC Hardware Description Language  VHSIC: Very High Speed Integrated Circuit 7/2/2015 2 R.H.Khade.

VHDL. What is VHDL? VHDL: VHSIC Hardware Description Language  VHSIC: Very High Speed Integrated Circuit 7/2/ R.H.Khade.
Simple Testbenches Behavioral Modeling of Combinational Logic

Simple Testbenches Behavioral Modeling of Combinational Logic
ECE 331 – Digital System Design Single-bit Adder Circuits and Adder Circuits in VHDL (Lecture #12) The slides included herein were taken from the materials.

ECE 331 – Digital System Design Single-bit Adder Circuits and Adder Circuits in VHDL (Lecture #12) The slides included herein were taken from the materials.
EE 367 – Logic Design Lecture #17

EE 367 – Logic Design Lecture #17

Similar presentations

Ads by Google