EMT 351/4 DIGITAL IC DESIGN Week # Synthesis of Sequential Logic 10

Contents Introduction Coding Styles of Sequential Synthesis Latch Models Flip-flop Models Memory Initialization General Sequential Circuit Synthesis

Introduction The target library used in synthesis has combinational and sequential components The target library will control the translation of a synthesizable Verilog code to hardware Example: If a description involves a latch and the target library does not have a latch, a latch will be built using gates or logic functions that available in the target library

Coding Styles of Sequential Synthesis Several typical styles of coding that will be discussed on what kind of hardware that they synthesized to: Latch models Flip-flop models Memory initialization General sequential circuit synthesis

Latch Models Level-sensitive (latched) behavior is characterized by an output which affected by input only while a control signal is asserted At other times, the input is ignored and the output remains its residual value Latches also inferred by the synthesis tool when it detects an incomplete ‘if’ / ‘case’ statement in a behavior

Example: Unwanted latch Synthesis result Incomplete statement based on 3 inputs Latch results from incomplete case statement Synthesis result

Latch Models Note: Use the right side code as an example Consider that the D-type latch is implemented on FPGA If the target library contains D-latch, it will be used to map the description, otherwise it will be built by wiring available target library hardware parts module latch (d, c, q, q_b) input d, c; output q, q_b; reg q, q_b; always@(c or d) if (c) begin q = d; q_b = ~d; end endmodule A D-type Latch

Representation of D-latch realization on Altera FPGA Latch Models (Cont..) LUT Flip-flop Logic gates Representation of D-latch realization on Altera FPGA (highlighted in gray)

Latch Models (Cont..) The FPGA consists of several logic gates, a look-up table (LUT), & a flip-flop (FF) The gray areas are parts of logic elements (LE) are used to implement the latch Implemented using programmed LUT Note that the FF (rectangular box on the right) is not used in this design

Flip-flop Models Register variable will be synthesized as the output of a flip-flop when its value is assigned synchronously with the edge of a signal If the event control expression is sensitive to the edge of more than one signal, an ‘if’ statement must be the first statement in the behavior The control signal (reset or set) must be declared explicitly in the branches of the ‘if’ statement (e.g. decode the reset condition first), whereas the synchronizing signal declared implicitly in the branches

Both red boxes cases generates the same synthesis product module jk_flop_1 (j, k, clock, rst, q, qb); input j, k, clock, rst; output q, qb; reg q; assign qb = ~q; always @ (posedge rst or posedge clock) begin if (rst == 1'b1) q = 1'b0; else // rst first if (j == 1'b0 && k == 1'b0) q = q; else if (j == 1'b0 && k == 1'b1) q = 1'b0; else if (j == 1'b1 && k == 1'b0) q = 1'b1; else if (j == 1'b1 && k == 1'b1) q = ~q; end endmodule Example: J-K Flip Flop case {j, k} 2'b00: q = q; 2'b01: q = 1'b0; 2'b10: q = 1'b1; 2'b11: q = ~q; Both red boxes cases generates the same synthesis product Synthesis result

Flip-flop Models (Cont..) Note: Use the right side code as an example Consider that this synthesizable code is implemented onto an FPGA If the FPGA FF does not meet the required behaviour, the logic around the FF would be used to realize the correct behaviour module latch (d, clk, q, q_b) input d, clk; output q, q_b; reg q, q_b; always@(posedge clk) begin q = d; q_b = ~d; end endmodule Positive-edge triggered DFF

Flip-flop Models (Cont..) The implementation of D-FF with synchronous reset on Altera FPGA (highlighted in gray)

Flip-flop Models (Cont..) Based on Figure A, the FF of the LE has asynchronous preset and clear inputs, & will be utilized if the input of the Verilog code required them However, if a synchronous control is required, the logic in FPGA’s LE i.e. LUT will be used (shown in Figure B)

Flip-flop Models (Cont..) The implementation of D-FF with asynchronous reset on Altera FPGA (highlighted in gray)

Memory Initialization Remember: ‘initial’ statements & memory initialization tasks are not synthesizable Most synthesis tool provide a mechanism for specifying ROM-based logic Example: Altera’s Quartus offers a memory block & its initialization file can be specified outside a Verilog module (separated)  this memory is directly mapped to the FPGA memory

Memory Initialization module gray_counter (d_in, clk, rst, ld, q); input [3:0] d_in; input clk, rst, ld; output q; reg [3:0] q, im_q; initial $readmemb (“mem.dat”, mem); always@(d_in or ld) begin if (ld) im_q = d_in; else im_q = mem[q]; end always@(posedge clk) if (rst) q <= 4’b0000; else q <= im_q; endmodule Example: Gary Code Counter Not synthesizable memory initialization Put memory file separately outside the module

General Sequential Circuit Synthesis Sequential circuit consist of combinational & register part For combinational part synthesis, must follow the rules for combinational logic synthesis For register parts, clocking rules & rules regarding to synchronous & asynchronous controls must be observed Individual bits of register parts in sequential circuit should refer to FF synthesis END