Proposed Tailed Biting Convolutional Codes for SFBCH Document Number: C80216m-09/0875r1 Date Submitted: 2009-04-27 Source: Changlong Xu, Hongmei Sun, Jong-Kae Fwu, Hujun Yin Intel Corporation Venue: IEEE Session #61, Cairo, Egypt. Re: TGm UL Control DG on UL Control Draft Amendment text Base Contribution: N/A Purpose: To be discussed and adopted by TGm for the 802.16m amendment. Notice: This document does not represent the agreed views of the IEEE 802.16 Working Group or any of its subgroups. It represents only the views of the participants listed in the “Source(s)” field above. It is offered as a basis for discussion. It is not binding on the contributor(s), who reserve(s) the right to add, amend or withdraw material contained herein. Release: The contributor grants a free, irrevocable license to the IEEE to incorporate material contained in this contribution, and any modifications thereof, in the creation of an IEEE Standards publication; to copyright in the IEEE’s name any IEEE Standards publication even though it may include portions of this contribution; and at the IEEE’s sole discretion to permit others to reproduce in whole or in part the resulting IEEE Standards publication. The contributor also acknowledges and accepts that this contribution may be made public by IEEE 802.16. Patent Policy: The contributor is familiar with the IEEE-SA Patent Policy and Procedures: <http://standards.ieee.org/guides/bylaws/sect6-7.html#6> and <http://standards.ieee.org/guides/opman/sect6.html#6.3>. Further information is located at <http://standards.ieee.org/board/pat/pat-material.html> and <http://standards.ieee.org/board/pat >.

Outline TBCC design for SFBCH Performance comparison Complexity comparison Summary

TBCC design for SFBCH 1.1 Basic parameters of proposed TBCC Native code rate 1/5 Generator polynomial 171, 133, 165, 117,127 in octal format Backward compatibility for 1/2 CC in 16e ODS better performance support rate matching Tail-biting Half complexity of Ericsson’s design K = 7 with 64 states in our design K = 8 with 128 states in Ericsson’s design

1.2 Structure of proposed TBCC

TBCC encoder with rate of 1/5

bit separation subblock interleaver All of the encoded bits shall be demultiplexed into five subblocks denoted A, B, C, D, and E. Support L information bits are input to the encoder. The encoder output bits shall be sequentially distributed into five subblocks with the first L encoder output bits going to the A subblock, the second L encoder output going to the B subblock, the third L to the C subblock, the fourth L to the D subblock, the fifth L to the E subblock. subblock interleaver First, the table for interleaving index with length of 128 entries was generated as follows. x = 1 : 128 index = (15x+32x2)mod 128 + 1 when the number of information bits is less than 128, the corresponding index table can be generated by removing the entries whose values are larger than the number of information bits.

bit grouping The channel interleaver output sequence shall consist of the interleaved A and B subblock sequences, followed by interleaved C, D, and E subblock sequences. bit selection Suppose L information bits are input to the encoder. The output sequence of bit group consists of 5L bits denoted as Here one parameter called is introduced to indicate the size of buffer used for repetition. Its value is less than 5L. If the output bits are M, the output sequence can be expressed as

1.3 Parameters for TBCC in SFBCH Information bits L = 7-24bits Buffer size 7-9 bits : 30bits 10, 11bits : 50bit, 55bits 12-24 bits : 60 bits Coded block size M : 60bits

2. Performance comparison -Parameters Channel Bandwidth 10MHz Over-sampling Factor 28/25 FFT Size 1024 Cyclic prefix (CP) ratio 1/8 Channel condition PB3, VA120, VA350 The number of antennas Tx:1, Rx:2 Modulation QPSK Channel estimation 2-D MMSE Tile structure 3 FMTs of 2x6 Pilot 2 pilot per FMT, Shifted pilot Receiver coherent detection, MLD demapper

TBCC vs. block codes under PB3

PB3 results for TBCC vs. block codes Pilot shifting is applied TBCC vs. block codes @PER=0.1 7bits: block codes (LG, Samsung) is 0.3dB better than Intel’s TBCC, 1dB than Ericsson’s TBCC 12bits: all performance are similar 24bits: Intel and Eric’s TBCC is around 0.4dB better than the other proposals Overall: Intel’s TBCC is preferred

SFBCH@VA120 7bits: block codes (LG, Samsung) is 1 dB better than Intel’s TBCC 12bits: all performance are similar 24bits: Intel & Eric’s TBCC is 0.5dB better than others Overall: Intel’s TBCC is preferred

SFBCH@VA350 7bits: block codes (LG, Samsung) is 0.7 dB better than Intel’s TBCC 12bits: all performance are similar 24bits: Intel, Eric’s TBCC are 0.3dB+ better than others Overall: Intel’s TBCC is preferred

2. Complexity comparison 2.1 TBCC vs. block codes Complexity of Block codes (N, K) Number of add 2K(N-1) Number of compare (real) 2k-1 Number of compare (binary) 2KN VA Complexity of TBCC with codeword length N, coding rate 1/R, Constraint length L Number of add N/R*2L*2*(R-1) Number of compare (real) (N/R+1)*2L Number of compare (binary) < N/R*2L*2*R=2N*2L Complexity of WAVA for TBCC Suppose max M iteration Complexity will be M*complexity of VA

2.2 Complexity comparison between linear block and TBCC using WAVA Algorithm Number of add Number of compare (real) Number of compare (binary) WAVA M*N/R*2L*2*(R-1) M*(N/R+1)*2^L M* 2N*2L MLD 2K(N-1) 2k-1 2KN

Parameters for complexity comparison between MLD and WAVA Parameters for MLD N = 60, K = 7,8,…,12 N = 30, two block of K = 6, 7, …, 12 Parameters for WAVA N = 60, R = 5, constraint length L = 7 (128states), M = 4 For simplification, do not consider complexity of puncturing, subblock interleaving For simplification, complexity of (60,12) is used for different number of information bits Among the three kinds of operations: add, compare (real), and compare (binary), the complexity of add is dominant. Thus, only add operator is necessary to be compared.

Complexity comparison between linear block and TBCC using WAVA

Comparison Results The average MLD decoding complexity 1.5 times over that of WAVA with K=8 (Ericsson) 3 times over that of WAVA with K=7(Intel) For case of 12bits and 24bits 5 times over that of Ericsson’s design 10 times over that of Intel’s design

Summary Performance Comparison Complexity Comparison Proposal of TBCC for SFBCH Native code rate of 1/5 Backward compatibility for ½ tbcc in 16e Performance Comparison 0.4 dB better than block code for 24bits Similar performance for 12 bits 0.3 dB worst than block code for 7 bits Always better than Ericsson’s design Complexity Comparison 1/10 of MLD for block codes with 7 bits 1/3 of MLD for block codes with average complexity Half complexity of Ericsson’s TBCC design Intel’s TBCC is preferred Better performance Lower complexity

Backup

AWGN Performance comparison

AWGN results for TBCC vs. block codes 7bits block codes (LG, Samsung) outperforms TBCC Intel’s TBCC better than Ericsson’s TBCC 12bits: all performance are similar 24bits: Intel’s TBCC is similar as Ericsson’ design @PER=0.1 Intel’s TBCC is around 0.8dB better block codes (LG, Samsung) @PER=0.1 Overall: Intel’s TBCC provides better performance over the other three proposals

Eb/No. vs. PER is gotten by Shifting SNR vs Eb/No. vs. PER is gotten by Shifting SNR vs. PER curves to the right by: 7.11dB for 7bits [10*log10(36/7 ) = 7.11dB ] 4.77dB for 12bits [10*log10(36/12) = 4.77dB ] 1.76dB for 24bits [10*log10(36/24) = .76dB ]