1. ARQ for IEEE 802.16m Document Number: IEEE C802.16m-09/0512
Date Submitted:
Source:
Muthaiah Venkatachalam Intel Corporation
Xiangying Yang Intel Corporation
Aran Bergman Intel Corporation
Venue: Re: TGm Call for Contributions and Comments on AWD: C802.16m-09/0012 for Session 60 in Vancouver, BC for UMAC/ARQ
Base Contribution: None
Purpose: Discussion and approval of the proposal into the IEEE m AWD
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2. Worst case of ARQ tpt Assume 16e ARQ 18x6 PRU => 96 data tones
QPSK1/2 is the worst case data MCS => 12Bytes/PRU
Minimum ARQ block size in 16m = 12B
Worst case tpt = 12B*1024/RTT
If RTT = 20msec, which is worst case
tpt = 5 Mbps

3. IMT.TECH Avg cell spectral efficiency
Test environment **
Downlink (b/s/Hz/cell)
Uplink (b/s/Hz/cell)
Indoor 3
2.25
Microcellular
2.6
1.80
Base coverage urban
2.2
1.4
High speed
1.1
0.7

4. ARQ Avg case throughputs for 16m
20 Mhz channel
DL tpt = 3*20 = 60Mbps
UL tpt = 2.25*20 = 45Mbps
If the DL tpt can be met, then the UL tpt can also be met.
Worst case assumption: total system tpt is gobbled up by 1 user!

5. ARQ proposal for 16m With 11bit BSN, worst case ARQ tpt is 5Mbps
This meets the IMT.TECH avg tpt requirements for DL (and UL)
Intel’s proposal for m ARQ:
Keep e ARQ intact
Use max of 15 bit BSN.

6. IMT.TECH Peak throughput
Error free conditions.
40Mhz channel
DL: 15 layer
UL: 6.75 layer
25% MAC overhead
DL tpt at ARQ layer = 450Mbps
UL tpt at ARQ layer = 202 Mbps
If the DL tpt can be met, then the UL tpt can also be met.
Worst case assumption: total system tpt is gobbled up by 1 user!

7. IMT peak tpt with Intel’s ARQ proposal
IMT peak tpt assumes error free conditions.
Max block size that can be used in error free conditions = 1024B.
With 1024B block, 15bit BSN and 20msec RTT,
ARQ tpt = 6.8Gbps!!!
Conclusion: Let us not change 16e ARQ unless we really need to!