The Associative Memory – AM = Bingo Dedicated device - maximum parallelism: Each pattern with private comparator Track search during detector readout Bingo scorecard Full custom 700 nm: 0,128 6L kpat/chip FPGA 350 nm: 0,128 6L kpat/chip standard cell 180 nm: 5,0 6L kpat/chip new for FTK 90 nm: ~60 8L kpat/chip new for FTK 65 nm: ~120 8L kpat/chip 2 Tiers 65 nm 2,5 D: 240 8L kpat/chip

Which banks we would like to have What we have now: Standard Cell 180 mm pattern/chip for 6-layer patterns, 2500 pattern/chip for 12-layer patterns       90 nm technology provides a factor 4 → 10000 patterns/chip Full custom cell provides at least a factor 2 → 20000 patterns/chip 8 layers instead of 12 provides a factor 1,5 → 30000 patterns/chip 1,5 x 1,5 cm**2 2D chip → 60000 patterns/chip Going to 65 nm → 120000 patterns/chip With a 2 D chip we gain a factor 50! 1 AMboard: 128 chips → ~15 Mpatterns per board 1 Crate: 16 AMboard → ~245 Mpatterns per crate 1,2 x 1,2 cm**2 2D chip → 80000 patterns/chip X 8 chips in a chain 20 bits → 600000 patterns/chip X 4 chips in a chain 19 bits → 300000 patterns/chip NEXT: NEW VERSION For both L1 & L2

Maximum Amount patterns/chip 2D 65 nm 1,5x1,5 cm^2 120 kpatt/chip 2 tiers 240 kpatt/chip Pipeline of 4 chips 960 kpatt/chip 20 bits/ pattern address Now we have 18 bits→2 x 2(I/O) = 4 new pads Hit Buses Now 6 buses <17:0> future 7 buses <14:0>

The CDF final AMchip architecture Pattern bank Add encoder kill Bus0[17:0] Bus1[17:0] Bus2[17:0] Bus3[17:0] Bus4[17:0] Bus5[17:0] 14:0 →3x6=18 free 15 for new bus + 3 free 19:0 19:0 → 2 bits x 2 missing

Summary of AMchip pinout Bus0[17-3:0] Bus5[17-3:0] Bus6[14:0] Bus0[17:0] Rev-en_ Debug[2:0] patt_add_a[17+2:0] patt_add_b[17+2:0] Wired_da_ SA-out_ SA-in_ DA-in_ DA-out_ -1 Opcode[3:0] Init clk

Costs 2 blocks Mini@sic: payed by Italy MPW run: TSMC 2010: 12 mm^2 80 kUSD → 6,7 kUSD/mm^2 UMC 2010: 4 mm x 4 mm 70 k€ → 4,37 k € /mm^2 12 mm^2 ~ 1/8 AMchip03 area in CDF → 7500 patterns/chip → 960 kpatterns/AMBoard With 2 blocks 160 kUSD → ~2 Mpatterns/AMBoard In 2012 could cost less – Academia Sinica can help on prize. Italy – Germany – USA – Academia Sinica (reduction) . For 2013: small production = 8+2 AMBoards = 1280 chips. How many wafers? How much for a wafer? we would like to be 4 funding agencies, especially for final step: Whole wafer Mask @time when a large area chip is needed: UMC 2010 90 nm: 555 kUSD TSMC 2010 65 nm: 1300-900 kUSD TSMC 2010 65 nm MLM 650-950 kUSD

Packaging chips together in the LAMB add_in add_out Pipelines of AM chips AMchip Control = GLUE

AMTOP Bus0 Bus1 Bus3 Bus2 AMBOTTOM Bus5 Bus4 add_in add_out LAMB AM INDI AMTOP Bus0 Bus1 Bus3 Bus2 AMBOTTOM Bus5 Bus4 PAT_ADD_IN [17:0] PAT_ADD_OUT REV_EN add_in add_out LAMB

6 bus (108 bits!) GLUE AM INDI Four 8-chips (top-bottom) pipeline FPGA VME INTERFACE ROAD CONNECTOR AM INDI Four 8-chips (top-bottom) pipeline FPGA I/O control FIFOS TRACKs ADD OUT [30:0] RECEIVERs & PIPELINE LAMB DRIVERs REGISTERs CONNECTORs (ROAD bus + CONNECTOR 6 HIT buses) HIT [17:0] HIT

Our Schedule TSMC 65 nm, low power, available as mini@sic (Vcc_core=1,2 V). 65 nm mini@sic 22,5 k€/block; 90 nm mini@sic 18,6 k€/block. "variable resolution" gives good results → early production of AM04 we missed the 90nm 2010 September run We propose to move directly to a 65 nm prototype. This is a preliminary schedule to produce new LAMBs for 2013: (1) Mini@sic submission: spring or october 2011. (2) delivery: ~february 2012 (3) tested ~June 2012 (4) MPW submission: from June 2012 (5) Delivery: from November 2012 (6) Tested: from February 2013 (7) MPW Production from February 2013 (8) Delivery from July 2013 (9) mounted on new Lambs from autumn 2013