COMP541 Memories - I Montek Singh Oct 10, 2016

Topics Overview of Memory Types Verilog descriptions of memories Read-Only Memory (ROM): PROMs, FLASH, etc. Random-Access Memory (RAM) Static today Dynamic next Verilog descriptions of memories

Types of Memory Many dimensions Look at ROM first to examine interface Read Only vs. Read/Write (or write seldom) Volatile vs. Non-Volatile Requires refresh or not Look at ROM first to examine interface

Non-Volatile Memory Technologies Mask (old)  ROM read-only memory Fuses (old)  PROM programmable read-only memory Erasable  EPROM erasable programmable read-only memory Electrically erasable  EEPROM electrically-erasable programmable read-only memory today called FLASH! used everywhere!

Details of ROM Memory that is permanent k address lines 2k items n bits

Notional View of Internals Main components: decoder for address decoding  select one row “wired-OR” per bit  OR’s together minterms ORing done by connecting outputs of effectively tristate buffers

Programmed Truth Table

ROM after programming Remember: OR is a “wired OR” output is 1 if any of the rows with an intact fuse is 1 0 otherwise

Mask ROMs Oldest technology Originally “mask” used as last step in manufacturing Specify metal layer (connections) Used for volume applications Long turnaround Used for applications such as embedded systems and, in the old days, boot ROM but cheap to mass produce!

Programmable ROM (PROM) Early ones had fusible links High voltage would blow out links Fast to program Single use

UV EPROM Erasable PROM Common technologies used UV light to erase complete device Took about 10 minutes Holds state as charge in very well insulated areas of the chip Nonvolatile for several (10?) years

EEPROM Electrically Erasable PROM Similar technology to UV EPROM Erased in blocks by higher voltage Programming is slower than reading Today’s flavor is called “flash memory” Digital cameras, MP3 players, BIOS Limited life Some support individual word write, some block Our boards have it: A flash memory chip on our Nexys boards Has a “boot block” that is carefully protected We will learn to use it in upcoming labs

How Flash Works Special transistor with floating gate This is part of device surrounded by insulation So charge placed there can stay for years Aside: some newer devices store multiple bits of info in a cell Interested in this? Let’s cover briefly

Flash Add an extra gate to an nMOS transistor a “float gate” below the actual control gate float gate is isolated from everything else can hold electrons for a while charge on float gate determines bit value stored electrons deposited  negative charge does not allow transistor to turn on if no electrons on float gate  transistor can be turned on by the control gate https://en.wikipedia.org/wiki/Flash_memory

Flash Add an extra gate to an nMOS transistor charge on float gate determines bit value stored float gate can be cleared using high voltage erased  ‘1’ value cannot erase individual bits: must clear an entire “block” or “page” can write individual bits for fast write speeds: must have empty blocks available speeds slows down as memory fills thus, garbage collection is important  overprovisioning used in SSDs https://en.wikipedia.org/wiki/Flash_memory

Read/Write Memories Flash is obviously writeable But not meant to be written rapidly (say at CPU rates) And often writing needs erasure of entire blocks For frequent writing, use RAM

Random Access Memories So called because it takes same amount of time to address any particular location Not entirely true for modern DRAMs, but somewhat true… First look at asynchronous static RAM reading and writing typically controlled by “handshakes” clock may still be present, but actions controlled by handshake signals

Simple View of RAM Typical parameters: some word size n some capacity 2k k bits of address line Need a line to specify reading or writing typically only one wire needed sometimes two separate ones

Example: 1K x 16 memory RAM comes in variety of sizes from 1-bit wide main issue is no. of pins available on chip Memory size often specified in bytes This would be 2KB memory 10 address lines (=1K locations) 16 data lines (=2 bytes/location)

Writing Sequence of steps Set up address lines Set up data lines Activate write line (e.g., maybe a positive edge)

Reading Steps Setup address lines Activate read line Data available soon for asynchronous memory: after simply a specified amount of time for synchronous memory: after a clock edge

Chip Select Enable: Usually a line to enable the chip Why?

Timing: Writing

Timing: Reading

Static vs. Dynamic RAM Different internal implementations: SRAM vs. DRAM DRAM: DRAM stores charge in capacitor Disappears after short period of time Must be refreshed Small size Higher storage density  larger capacities SRAM: SRAM easier to use Uses transistors (think of it as latch) Faster More expensive per bit Smaller sizes

Structure of SRAM Internally, each bit stored in a “latch” One memory cell per bit Cell consists of a few transistors Not really a latch made of NANDs/NORs, but logically equivalent Behaves like an SR latch Control logic also need extra logic around the latch to make it work like a memory cell

Structure of SRAM Several optimized circuits often used replace a full-fledged SR latch with something simpler, smaller, faster… Not really a latch made of NANDs/NORs, but logically equivalent Behaves like an SR latch e.g., a simpler 6-transistor memory cell wordline  Select (bitline, bitline’)  (B, B’) as well as (C, C’)

Example: A Simple Organization Note: In reality, more complex Only one word-line is “on” at a time

Zoom in: A single bit slice Operation: Cells connected to form 1 bit position (column) Word Select enables one latch from address lines only this cell is writable only this cell is read B (and B’) set by: Read/Write’ Data In Bit Select Outputs are C and C’ if enabled, output value of cell if disabled, typically output floating

Let’s look at a single bit cell Example: Z 1 Z

Bit Slices and Modules Entire column of cells Module called a bit slice basically a 1-bit wide memory! Module module refers to a single chip of memory 1-bit wide memory chips are quite common!

Inside an SRAM Bit Cell Actual implementation does not use a real SR latch! a tinier approximation is used logically behaves very much like an SR latch but much smaller and faster!

16 X 1 RAM “Chip” Now shows address decoder selects appropriate location

Row/Column Layout For larger RAMs: Typically: decoder becomes pretty big also run into chip layout issues Typically: larger memories use “2D” matrix layout see next slide

16 X 1 RAM as 4 X 4 Array Two decoders Address just broken up Row Column Address just broken up Not visible from outside on SRAMs

Not the same as 8 X 2 RAM! Minor change in logic and pins Spot the difference!

Spot the difference!

Realistic Sizes Example: 256Kb memory organized 32K X 8 Single-column layout would need 15-bit decoder with 32K outputs! Better organization: A 2D (i.e., square) layout with: 9-bit row and 6-bit column decoders

SRAM Performance Latency and Throughput important Current ones have cycle times in low nanoseconds say 1-2ns (top-end ones even lower) Used as cache (typically on-chip or off-chip secondary cache) Sizes up to 8Mbit or so for fast chips Expensive ones can go a bit bigger Energy/power SRAMs also better for low power vs. DRAMs

Wider Memory What if you don’t have enough bit width? use multiple chips and side-by-side

Larger/Wider Memories Made up from sets of chips Consider a 64K by 8 RAM our building block

Larger Let’s build a larger memory 256K X 8 Decoder for high-order 2 bits Selects chip Look at selection logic Address ranges Tri-state outputs

SystemVerilog Behavioral descriptions of: ROM, single-ported RAM, dual-ported RAM, etc.

SystemVerilog: 1-port RAM RAM example single-ported  one address (for reading and writing) whether read or written is determined by “write enable” clock all writes take place on clock tick reads are asynchronous i.e., output after a propagation delay without waiting for a clock tick clock addr din dout wr 1-port RAM

SystemVerilog: 1-port RAM logic [Dbits-1:0] mem [Nloc-1:0]; always_ff @(posedge clock) if(wr) mem[addr] <= din; assign dout = mem[addr]; The actual storage where data resides Write operation on clock tick if write enabled Reading is asynchronous, no clock involved clock addr din dout wr 1-port RAM

SystemVerilog: 2-port RAM RAM example 2 ports one read-write port (using addr1) one read-only port (using addr2) 2 outputs: dout1 and dout2 only one data input: din clock read-write: addr1 din dout1 wr 2-port RAM read-only: addr2 dout2

SystemVerilog: 2-port RAM logic [Dbits-1:0] mem [Nloc-1:0]; always_ff @(posedge clock) if(wr) mem[addr1] <= din; assign dout1 = mem[addr1]; assign dout2 = mem[addr2]; The actual storage where data resides Write operation on clock tick if write enabled Reading is asynchronous, no clock involved clock read-write: addr1 din dout1 wr 2-port RAM read-only: addr2 dout2

SystemVerilog: register file 3 ports two read-only ports (using ReadAddr1 and ReadAddr2) one write-only port (using WriteAddr) 2 outputs: ReadData1 and ReadData2 one data input: WriteData special case: reading $0 always returns 0 clock ReadAddr1 WriteData ReadData1 wr 3-port register file ReadAddr2 ReadData2 WriteAddr

SystemVerilog: register file logic [Dbits-1:0] rf [Nloc-1:0]; always_ff @(posedge clock) if(wr) rf[…] <= …; assign ReadData1 = … ? … rf[…]; The actual storage where data resides Write operation on clock tick if write enabled Reading is asynchronous, no clock involved Reading $0 must always return 0 clock ReadAddr1 WriteData ReadData1 wr 3-port register file ReadAddr2 ReadData2 WriteAddr Skeleton only. You fill in the details (Lab 8).

SystemVerilog: memory initialization Specify a file that contains initial values one value per line: hex or binary use $readmemh for hex use $readmemb for binary logic [Dbits-1:0] mem[Nloc-1:0]; initial $readmemh(“mem_data.txt”, mem, 0, Nloc-1); always_ff @(posedge clock) … assign … Specifies the file that contains initial values

SystemVerilog: ROM example single-ported read-only, no writing no clock needed reads are asynchronous i.e., output appears after a propagation delay without waiting for a clock tick logic [Dbits-1:0] mem [Nloc-1:0]; initial $readmemh(“mem_data.txt”, mem, 0, Nloc-1); assign dout = mem[addr]; Read operation only, no writes

Summary Today we looked at: Next topic: Quick look at non-volatile memory Static RAM SystemVerilog templates for memories Next topic: Dynamic RAM Complex, largest, cheap Much more design effort to use