CSCI206 - Computer Organization & Programming

Slides:



Advertisements
Similar presentations
Henk Corporaal TUEindhoven 2011
Advertisements

Review of the MIPS Instruction Set Architecture. RISC Instruction Set Basics All operations on data apply to data in registers and typically change the.
MIPS assembly. Review  Lat lecture, we learnt  addi,  and, andi, or, ori, xor, xori, nor,  beq, j, bne  An array is stored sequentially in the memory.
CS/COE0447 Computer Organization & Assembly Language
Branches Two branch instructions:
Chapter 2 — Instructions: Language of the Computer — 1 Branching Far Away If branch target is too far to encode with 16-bit offset, assembler rewrites.
ECE 15B Computer Organization Spring 2010 Dmitri Strukov Lecture 5: Data Transfer Instructions / Control Flow Instructions Partially adapted from Computer.
1 Lecture 4: Procedure Calls Today’s topics:  Procedure calls  Large constants  The compilation process Reminder: Assignment 1 is due on Thursday.
The University of Adelaide, School of Computer Science
Lecture 8: MIPS Instruction Set
Lec 9Systems Architecture1 Systems Architecture Lecture 9: Assemblers, Linkers, and Loaders Jeremy R. Johnson Anatole D. Ruslanov William M. Mongan Some.
Assembly Process. Machine Code Generation Assembling a program entails translating the assembly language into binary machine code This requires more than.
Comp Sci instruction encoding 1 Instruction Encoding MIPS machine language Binary encoding of instructions MIPS instruction = 32 bits Three instruction.
Instruction Representation II (1) Fall 2007 Lecture 10: Instruction Representation II.
Computer Structure - The Instruction Set (2) Goal: Implement Functions in Assembly  When executing a procedure (function in C) the program must follow.
RISC Concepts, MIPS ISA and the Mini–MIPS project
Lecture 5 Sept 14 Goals: Chapter 2 continued MIPS assembly language instruction formats translating c into MIPS - examples.
Instruction Representation II (1) Fall 2005 Lecture 10: Instruction Representation II.
ECE 232 L5 Assembl.1 Adapted from Patterson 97 ©UCBCopyright 1998 Morgan Kaufmann Publishers ECE 232 Hardware Organization and Design Lecture 5 MIPS Assembly.
Data Transfer & Decisions I (1) Fall 2005 Lecture 3: MIPS Assembly language Decisions I.
Memory and Addressing How and Where Information is Stored.
Lecture 8. MIPS Instructions #3 – Branch Instructions #1 Prof. Taeweon Suh Computer Science Education Korea University 2010 R&E Computer System Education.
CSCI 136 Lab 1: 135 Review.
Chapter 10 The Assembly Process. What Assemblers Do Translates assembly language into machine code. Assigns addresses to all symbolic labels (variables.
April 23, 2001Systems Architecture I1 Systems Architecture I (CS ) Lecture 9: Assemblers, Linkers, and Loaders * Jeremy R. Johnson Mon. April 23,
Small constants are used quite frequently (50% of operands) e.g., A = A + 5; B = B + 1; C = C - 18; Solutions? Why not? put 'typical constants' in memory.
Chapter 2 Decision-Making Instructions (Instructions: Language of the Computer Part V)
9/29: Lecture Topics Conditional branch instructions
Computer Organization Instructions Language of The Computer (MIPS) 2.
Computer Organization CS224 Fall 2012 Lessons 7 and 8.
Chapter 2 — Instructions: Language of the Computer — 1 Memory Operands Main memory used for composite data – Arrays, structures, dynamic data To apply.
Chapter 2 — Instructions: Language of the Computer — 1 Conditional Operations Branch to a labeled instruction if a condition is true – Otherwise, continue.
Branch Addressing op rs rt address address beq $s1, $s2, Label if ($s1 = =$s2) go to Label 6 bits 5 bits 5 bits 16 bits effective 32 bit address.
The Assembly Process Computer Organization and Assembly Language: Module 10.
DR. SIMING LIU SPRING 2016 COMPUTER SCIENCE AND ENGINEERING UNIVERSITY OF NEVADA, RENO Session 11 Conditional Operations.
Control Structures Computer Organization I 1 October 2009 © McQuain, Feng & Ribbens Conditional Control Structure if ( i < j ) goto A; else.
CSCI-365 Computer Organization Lecture Note: Some slides and/or pictures in the following are adapted from: Computer Organization and Design, Patterson.
Computer Architecture & Operations I
Prof. Hsien-Hsin Sean Lee
Lecture 6: Assembly Programs
MIPS Instruction Set Advantages
MIPS Coding Continued.
RISC Concepts, MIPS ISA Logic Design Tutorial 8.
Conditional Branches What distinguishes a computer from a simple calculator is its ability to make decisions Decisions are made using the if statement,
Lecturer PSOE Dan Garcia
Computer Architecture (CS 207 D) Instruction Set Architecture ISA
Pick up the handout on your way in!!
CSCI206 - Computer Organization & Programming
Henk Corporaal TUEindhoven 2010
MIPS Instructions.
MIPS Instruction Encoding
ECE232: Hardware Organization and Design
MIPS Instruction Encoding
Lecture 7: Examples, MARS, Arithmetic
Instruction encoding The ISA defines Format = Encoding
MIPS coding.
MIPS Coding.
The University of Adelaide, School of Computer Science
Other ISAs Next, we’ll first we look at a longer example program, starting with some C code and translating it into our assembly language. Then we discuss.
Flow of Control -- Conditional branch instructions
Lecturer SOE Dan Garcia
Lecture 6: Assembly Programs
MIPS Assembly.
Flow of Control -- Conditional branch instructions
MIPS Coding Continued.
Program Assembly.
9/27: Lecture Topics Memory Data transfer instructions
Conditional Control Structure
Conditional Branching (beq)
Control Flow and Arrays
Presentation transcript:

CSCI206 - Computer Organization & Programming Pseudo-Instructions and Addressing Data zyBook: 5.8, 5.9

Pseudo-instructions beq $t, $s, label What is a pseudo-instruction? A pseudo-instruction is not a real MIPS instruction, but one can use it as if it were. For example, we know these two MIPS instructions beq $t, $s, label bne $t, $s, label But we don’t have something like blt $t, $s, label Or the like

MIPS Pseudo-instructions MIPS provides a set of such pseudo-instructions to make programmers’ life easier. Typically these pseudo-instructions are translated into real instruction at the assembly time For example, blt $t, $s, label Can be implemented as slt $at, $t1, $t2 bne $at, $zero, label

One more example li $t0, 0x8C828A43 Can be implemented as lui $at, 0x8c82 ori $t0, $at, 0x8a43 [let’s do the worksheet]

Registers Addressing data in a register Encode the register number (0-31) in the machine instruction R/I formats

Immediates Immediate data can be encoded in an I type instruction this data is implicitly addressed what are the limitations?

32-bit Values from Immediates step 1: lui - load upper immediate lui $t0, 0x00FF step 2: ori - or immediate ori $t0, $t0, 0xFF00 final result in $t0 0000 0000 1111 1111 1111 1111 0000 0000 which is 0x00FFFF00 MIPS optimizes for the common case, small immediate values two instructions are handle the other (less common) cases.

Basic Program Memory Map Local (automatic) variables inside functions; activation records (recursion); unsafe to share between functions / modules Dynamic (runtime) allocation Dynamically allocated memory; safe to share between functions / modules Global variables Static (compile time) allocation Your program’s compiled machine code

Base + displacement addressing lw/lh/lb sw/sh/sb Construct a memory address from a base address in a register plus some immediate offset Useful for variables top of stack/heap in $sp/$gp register, immediate value selects offset Useful for arrays beginning of array in a register, immediate value selects the index

PC-Relative Addressing (branches) PC is the Program Counter, it is the address of the instruction being executed. I-format instruction provides a 16 bit offset, relative to the next instruction. Good for short branches (local loops, if, case, etc). Not enough bits for function calls (can’t jump very far away).

MIPS Branch Distance The branch immediate address is a sign extended (2's complement) value added to the current PC Since we are dealing with instructions that must be word aligned (32-bit), the last 2-bits are assumed to be 00, therefore a branch can reach +0x1fffc or -0x20000 bytes! (that is +32767 or -32768 instructions)

Pseudo-direct Addressing J-type instructions contain a 26-bit word address (unsigned) (28-bit byte address), 2^28 == 256 MB range This leaves the upper 4-bits unaccounted for Uses the upper 4-bits of the next PC value This is enough for most programs How could you jump beyond the 256 MB?

MIPS Addressing