서강대학교 기계공학과 최범규(Choi, Bumkyoo) Micromachining 기술 I (Silicon Based) 서강대학교 기계공학과 최범규(Choi, Bumkyoo)

Oxidation Fundamental process in all silicon device fabrication Used for (i) passivation of the silicon surface (i.e., the formation of a chemically and electronically stable surface) (ii) masking of diffusion and ion implantation (0.5-1µm) (iii) dielectric films (50-200Å) (iv) an interface layer between the substrate and other materials

A native oxide : about 20Å thick Process parameter : temp. time Si+O2  SiO2 for dry oxygen Si+2H2O  SiO2+2H2 for water vapor

The oxide expands to fill a region approximately SiO2 Original surface 0.54 tox 0.46 tox Si wafer The oxide expands to fill a region approximately 54% above and 46% below the original surface of the wafer

Diffusion The deposition of a high concentration of the desired impurity on the silicon surface At high temperature (900 - 1200C), the impurity atoms move from the surface into the silicon crystal

Without vacancy “rapid” Substitutional diffusion Interstitial diffusion Interstitial impurity atom Substitutional impurity atom vacancy Need vacancy “slow” “good” Without vacancy “rapid” Speed Control * donor 나 acceptor가 되기 위해서 반드시 substitutional site를 차지 해야 함. Need activation  annealing

Governing equation Fick’s first law J : the particle flux (particle flow/unit area) N : the particle concentration Fick’s second law (from the continuity equation) (*) CSD : the impurity concentration is held constant at the surface of the wafer LSD : the dose Q remains constant throughout the process

Constant-Source Diffusion Limited-Source Diffusion Sol’n of Eq(*) No : impurity concentration at wafer surface(x=0) Q0 : total # of impurity atom per unit area (dose) Dt “erfc” Impurity concn. N(x) Distance from surface x distribution “Gaussian” x No1 No2 No3 Dose (Q)

Practical diffusion Two-step diffusion  Predeposition of impurity source (CSD) : D1t1  Impurity drive-in (LSD) : D2t2 If D1t1 >>D2t2, the resulting impurity profile is approximated by erfc D1t1 <<D2t2, the resulting impurity profile is approximated by Gaussian

Ion Implantation Ion implanter : a high-voltage particle accelerator producing a high velocity beam of impurity ions which penetrate the surface of Si wafer Mass spectrometer Ion source Accelerator X-axis scanner Y-axis scanner Target

Ion source : high voltage (25kV) produces a plasma containing the desired impurity as well as other undesired species Mass spectrometer : an analyzer magnet bends the ion beam through a right angle to select the desired impurity ion High-voltage accelerator : adds energy to the beam (∼175kV) and accelerates the ions to their final velocity Scanning system : X-and Y-axis deflection plates are used to scan the beam across the wafer to give a uniform implantation and the desired dose

Advantage (cf. Diffusion) 1. Low temperature 2. Process flexibility mask material (SiO2, PR, Nitride, Metals) wide range of impurity species 3. Process stability dose control pure dopant species (mass spectrometer) Disadvantage expensive, bulky facility (1-2 million), source damage

Thin film deposition 1. Evaporation The desired metals are heated to the point of vaporization and evaporate to form a thin film (high temp., low pressure) E-beam heating target

2. Sputtering (Physical) Sputtering is achieved by bombarding a target with energetic ions. (보통 Ar+) Atoms at the surface of the target are knocked loose and transported to the substrate, where deposition occurs (metal and nonmetal alloy) Ar+ target source

3. CVD (Chemical Vapor Deposition) CVD forms thin films on the surface of a substrate by thermal decomposition and/or reaction of gaseous compounds. The desired material is deposited directly from the gas phase onto the surface of the substrate To exhaust system Wafers Susceptor N2 H2 SiCl4+ H2 HCl Dopant+ H2

4. Epitaxy CVD processes can be used to deposit silicon onto the surface of a Si wafer under appropriate conditions, the Si wafer acts as a good crystal, and a single-crystal silicon layer is grown on the surface the wafer

Step coverage CVD > Sputtering > Evaporation CVD Evaporation source CVD Evaporation Sputtering CVD > Sputtering > Evaporation

Bulk-Micromachining Silicon Bulk-micromachining Two key capabilities Wet (chemical) or dry(plasma) etching of silicon substrate, in combination with masking film (etch-resistant layers) to form micromechanical structures Two key capabilities 1. Anisotropic etchants of silicon : EDP (ethylen-diamine and pyrocatechol), KOH preferentially etch single crystal silicon along given crystal planes 2. Etch masks and etch-stop techniques are available in conjunction with silicon anisotopic etchants

Isotropic etching : uniform at all orientations Anisotropic etching : depend on crystal orientation Isotropic with agitation Isotropic w/o agitation <100> <110> 54.75° Anisotropic on (100) surface Anisotropic on (110) surface

Etchant and Etch masks 1) Isotropic etchant HF : HNO3 : CH3COOH = 7 : 3 : 1 (HNA system) mask-SiO2, Si3N4 2) Anisotropic etchant EDP (Ethylene Diamine and Pyrocatechol) KOH * Etch Rate R(100) R(110) R(111) mask EDP 50 : 30 : 1 SiO2(2Å/min),Si3N4 Au,Cr,Ag,Cu,Ta KOH 100 : 600 : 1 Si3N4, SiO2 (14Å/min) * KOH 사용시 EDP 때보다 Oxide의 두께는 훨씬 두꺼워야 한다

Etch rate 1) Agitation increases the supply of reactant material to the surface, thus increasing the etch rate (stirring) 2) Temperature 3) The supply of minority carriers to the surface 4) Creation of electron-hole pairs on the surface (by illumination or currents) 5) Substrate-crystal orientation, type and concentration of doping atoms, lattice defects, and surface structure

Etch stop & thickness control 1. Dopant dependent etch stop The etching process is fundamentally a charge-transfer mechanism and etch rates depend on dopant type and concentration Highly doped material might be expected to exhibit higher etch rate because of the greater availability of mobile carriers etch rate 1-3 µm/min at p or n 1018/cm3 essentially zero less than 1017/cm3 Si heavily doped with boron (7x1019cm-3) reduce the etch rate by about 1/20 with KOH & EDP (p+) 2. Electrochemical etch stop 3. p-n junction etch stop 4. Various etch stop method (case by case)

Dry etching Involves the removal of substrate materials by gaseous etchants without wet chemicals or rinsing Plasma etching Plasma is a neutral ionized gas carrying a large number of free electrons and positively charged ions A common source of energy for generating plasma is a RF source The process involves adding a chemically reactive gas such as CCl2F2 to the plasma The reactive gas produces reactive neutrals when it is ionized in the plasma The reactive neutrals bombard the target on both the sidewalls as well as the normal surface, whereas the charged ions bombard only the normal surface of the substrate Etching of the substrate materials is accomplished by the high energy ions in the plasma bombarding the substrate surface with simultaneous chemical reactions between the reactive neutral ions and the substrate material

Dry etching (2) Plasma etching (cont’d) The high energy reaction causes local evaporation, and thus results in the removal of the substrate material Conventional dry etching is a very slow process at a rate of about 0.1 mm/min or 100 A/min Plasma etching can increase the etching rates in the order of 2000A/min by increasing the mean free path of the reacting gas molecules in the depth to be etched Plasma etching is normally performed in high vacuum Dry etching is typically faster and cleaner than wet etching Like wet etching, it also suffers the shortcoming of being limited to producing shallow trenches For dry etching, the aspect ratio is less than 15 Another problem is the contamination of the substrate surface by residues

Deep Reactive Ion Etching (DRIE) Despite the significant increase in the etching rate and the depth of the etched trench that can be achieved with the use of plasma, the etched walls in the trenches remain at a wide angle (q) to the depth DRIE is a process that produces the high aspect ratio MEMS with virtually vertical walls ( ) The DRIE process differs from plasma etching in that it produces thin protective films of a few micrometers on the sidewalls during the etching process

Deep Reactive Ion Etching (DRIE) It involves the use of a high density plasma source, which allows alternating processes of plasma (ion) etching of the substrate material and the deposition of etching protective material on the sidewalls Suitable etching protective materials is SiO2. Polymers are also frequently used for this purpose Recent developments have substantially improved the performance and Si substrates with A/P over 100 was achieved with

Surface - Micromachining Machining of thin film to make microstructures cf) Bulk-micromachining : Silicon wafer Surface-micromachining : Thin film on Si wafer / free standing from substrate IC-fabrication : Surface of Si wafer / fixed on substrate *The ultimate success of surface-micromachined devices are determined by the availablility of thin films of high quality and good stability

1. Thin film deposition 2. Thin film patterning Evaporation Sputtering CVD 2. Thin film patterning Subtractive process : Wet chemical etching Dry etching cf) Bulk micromachining 에서는 (orientation-dependant) 결정면에 따라 etching 속도가 다른 것을 이용 Surface micromachining 은 material-dependent (selective etching) Additive process : Wet electroplating Dry lift off

Subtractive : film 올리고 필요 없는 부분 제거 Additive : 필요한 부분만 film 생성 PR metal PR Electroplating Lift-off

Etchants

Sacrificial Materials Thin film materials 1. Poly-Si and amorphous Si 2. Single-crystal Si 3. Si nitride (Si3N4) 4. Si dioxide (SiO2) 5. Organic films : Polymide Sacrificial Materials 1. LTO (Low-Temperature Oxide) 2. PSG (Phosphorsilicate glass) 3. Polymide or photoresist

Surface-Micromachining Sample