Class Exercise 1B.

Slides:



Advertisements
Similar presentations
Tutorial 2 Sequential Logic. Registers A register is basically a D Flip-Flop A D Flip Flop has 3 basic ports. D, Q, and Clock.
Advertisements

Class Exercise 1A.
Registers and Counters. Register Register is built with gates, but has memory. The only type of flip-flop required in this class – the D flip-flop – Has.
Multiplexors Sequential Circuits and Finite State Machines Prof. Sin-Min Lee Department of Computer Science.
1 Sequential Circuits Dr. Pang. 2 Outline Introduction to sequential circuits Basic latch Gated SR latch and gated D latch D flip-flop, T flip-flop, JK.
Princess Sumaya Univ. Computer Engineering Dept. Review:
2-1 ECE 424 Design of Microprocessor-Based Systems Haibo Wang ECE Department Southern Illinois University Carbondale, IL Fundamentals of Digital.
ENGIN112 L20: Sequential Circuits: Flip flops October 20, 2003 ENGIN 112 Intro to Electrical and Computer Engineering Lecture 20 Sequential Circuits: Flip.
CS 151 Digital Systems Design Lecture 20 Sequential Circuits: Flip flops.
Fall 2007 L16: Memory Elements LECTURE 16: Clocks Sequential circuit design The basic memory element: a latch Flip Flops.
Sequential Circuit Introduction to Counter
A.Abhari CPS2131 Registers A register is a group of n flip-flops each of them capable of storing one bit of information There are two types of registers:
Princess Sumaya Univ. Computer Engineering Dept. Review:
1 Sequential Circuits Registers and Counters. 2 Master Slave Flip Flops.

Objectives: Given input logice levels, state the output of an RS NAND and RS NOR. Given a clock signal, determine the PGT and NGT. Define “Edge Triggered”
1 Registers and Counters A register consists of a group of flip-flops and gates that affect their transition. An n-bit register consists of n-bit flip-flops.
SEQUENTIAL CIRCUITS Component Design and Use. Register with Parallel Load  Register: Group of Flip-Flops  Ex: D Flip-Flops  Holds a Word of Data 
Computer Organization & Programming Chapter 5 Synchronous Components.
Computer Architecture and Organization Unit -1. Digital Logic Circuits – Logic Gates – Boolean Algebra – Map Simplification – Combinational Circuits –
CO5023 Latches, Flip-Flops and Decoders. Sequential Circuit What does this do? The OUTPUT of a sequential circuit is determined by the current output.
1 KU College of Engineering Elec 204: Digital Systems Design Lecture 22 Memory Definitions Memory ─ A collection of storage cells together with the necessary.
ECE 545—Digital System Design with VHDL Lecture 1
D Flip Flop. Also called: Delay FF Data FF D-type Latches ‘Delayed 1 Clock Pulse’
Registers ECEn/CS 224.
George Mason University Class Exercise 1B. 2ECE 448 – FPGA and ASIC Design with VHDL Rules If you believe that you know a correct answer, please raise.
Counters and registers Eng.Maha Alqubali. Registers Registers are groups of flip-flops, where each flip- flop is capable of storing one bit of information.
1 Registers A register is a group of n flip-flops each of them capable of storing one bit of information There are two types of registers: parallel and.
DIGITAL LOGIC CIRCUITS 조수경 DIGITAL LOGIC CIRCUITS.
Appendix C Basics of Logic Design. Appendix C — Logic Basic — 2 Logic Design Basics §4.2 Logic Design Conventions Objective: To understand how to build.
Sequential Logic Design
Computer Science 210 Computer Organization
Computer Architecture & Operations I
Supplement on Verilog FF circuit examples
DIGITAL LOGIC CIRCUITS
Digital Logic & Design Dr. Waseem Ikram Lecture 39.
EMT 351/4 DIGITAL IC DESIGN Week # Synthesis of Sequential Logic 10.
CPU Sequencing 6/30/2018.
Sequential Logic Counters and Registers
Sequential Circuit: Counter
Basics of digital systems
DR S. & S.S. GHANDHY ENGINEENRING COLLEGE
DIGITAL LOGIC CIRCUITS
Computer Science 210 Computer Organization
Flip-FLops and Latches
Introduction to Sequential Logic Design
DIGITAL ELECTRONICS THEME 7: Register structures – with parallel input, with serial input. Shift registers – reversible, cycle. Register structures are.
Latches and Flip-flops
Lecture 16 PicoBlaze I/O & Interrupt Interface
Instructor: Alexander Stoytchev
Computer Science 210 Computer Organization
Elec 2607 Digital Switching Circuits
COE 202: Digital Logic Design Sequential Circuits Part 4
Digital Logic & Design Dr. Waseem Ikram Lecture 40.
Computer Architecture and Organization: L02: Logic design Review
ECE 545—Digital System Design with VHDL Lecture 1
CSE 370 – Winter Sequential Logic-2 - 1
Lecture 17 Logistics Last lecture Today HW5 due on Wednesday
Instructor: Alexander Stoytchev
Instructor: Alexander Stoytchev
Class Exercise 1A.
Sequential Logic.
Switching Theory and Logic Design Chapter 5:
Systems Architecture I
14 Digital Systems.
RTL Design Methodology Transition from Pseudocode & Interface
CHAPTER 18 Circuits for Arithmetic Operations
Lecture 17 Logistics Last lecture Today HW5 due on Wednesday
Reference Chapter 7 Moris Mano 4th Edition
(Sequential-Circuit Building Blocks)
Presentation transcript:

Class Exercise 1B

Rules If you believe that you know a correct answer, please raise your hand I will select one or more students (independently whether an answer given by the first student is correct or incorrect) Please, identify yourself by first name and give an answer Correct answer = 1 bonus point 8

Problem 1 What is a difference between combinational logic and sequential logic?

Problem 2 What is a difference between Latches and Flip-flops?

Problem 3 What is a difference between: Reset active high vs. Reset active low Asynchronous Reset vs. synchronous Reset?

Problem 4 What is a register?

Problem 5 Draw a block diagram of the digital circuit with the following interface and functionality: Interface: Din – 8-bit data input Dout – 8-bit data output Addr – 2-bit address of the location (register) where input data is stored or output data is read from RW – control signal, 0=read, 1=write Clk – clock

Problem 5 (cont.) Functionality: If RW = 1, then the output Dout is set to the high impedance state, and at the next rising edge of the clock, data from the input Din is stored in the internal location given by the address Addr. If RW = 0, data from the location given by the address Addr is transferred to the output Dout, and the contents of the internal memory (registers) does not change.

Problem 5 (cont.) Assume that the internal memory is implemented using registers. Use only medium scale components, such as registers, multiplexers, encoders, decoders, buffers, etc.

Problem 6 Draw internal structure of a 4-bit Shift Register with Enable and Parallel Load

Problem 7 What is a difference in terms of the required inputs and outputs between ROM and RAM of the same size (e.g. 2m x n)?

Problem 8 What is a difference between a single-port and dual-port RAM? What operations are allowed in the dual-port RAM?