Partial Reconfigurable Designs Multi-layer Floorplanning Max Walton

Outline Introduction Floorplanning Model Proposed Floorplanner Results Challenges Floorplanning Model Proposed Floorplanner Data Representation Cost Functions Moves Matching Results Jun 12, 2008 Max Walton

Introduction Partial Reconfiguration Issues Difference-based (used in this paper) Module-based Issues Reconfiguration overhead Time issues Placement Jun 12, 2008 Max Walton

Floorplanning Terminology Static Module AKA: fixed module A module that will not be reconfigured Non-static module AKA: reconfigured modules Modules that will be reconfigured between designs Jun 12, 2008 Max Walton

Introduction: Challenges Reuse Matching Which components overlap during configuration? Reuse Placement Where do the components need to be placed? Reuse Interface How are such components connected to reconfigurable regions? Jun 12, 2008 Max Walton

Floorplanning Placing components on a chip Differs from placement by only placing large sized components on chip Does not look at logic Complements Placement Outputs coordinates defining positions of block on device Jun 12, 2008 Max Walton

Floorplanning Three types of floorplanning Independent Dependent Combined Jun 12, 2008 Max Walton

Floorplanning Simulated Annealing Based Fixed Outline Floorplanning Constrain design in rectangular shapes of fixed aspect ratio Parquet Area Wirelength Aspect Ratio Jun 12, 2008 Max Walton

Model Frames Span n columns Module spans contiguous set of frames (hor/vert) Time to reconfigure linear function of number of frames to be reconfigured Minimize number of frames by placing fixed and reconfigurable parts in separate frames Jun 12, 2008 Max Walton

Assumptions Complete Sequence of Designs is known No Data Dependency Between Designs / Input and Output Buffered in Static region Soft blocks Changing of aspect ratio is allowed Block can be placed anywhere on device Heterogeneous floorplanning out of scope All designs are timing critical Jun 12, 2008 Max Walton

Reusable Components Keep interconnects outside of static regions Use of whitespace for interfaces Maximize A1,2 and Areused Jun 12, 2008 Max Walton

Proposed Floorplanner (FFPR) Built from Parquet floorplanner Routing congestion Total Frames Handles multiple designs simultaneously Jun 12, 2008 Max Walton

Definition Given design D1 with a set of modules M1 = {m1, …, mn1} and corresponding connectivity, Given design D2 with a set of modules M2 = {m1, …, mn2} and corresponding connectivity, Given a set of common modules between the two designs M12, Floorplan each design such that the total area and wirelength in each design is minimized as well as total reconfiguration area is minimized. Extensible to k>2 reconfigurable designs Jun 12, 2008 Max Walton

FFPR Jun 12, 2008 Max Walton

FFPR: Data Representation Placement by Sequence Pairs Exact placement found with horizontal and vertical graphs Algorithm runs in O(n2) Jun 12, 2008 Max Walton

FFPR: Data Representation Two-layer Sequence pair Non-static have no left-right or up-down relationship between each other Horizontal and vertical graphs are connected through static nodes only Jun 12, 2008 Max Walton

FFPR: Data Representation Jun 12, 2008 Max Walton

FFPR: Cost Functions Scaling factors Area Sum to 1 Represent respective weights of area, aspect ratio, frames, wirelength, congestion Area Minimum bounding box encompassing all designs Negative if new area is less than current Jun 12, 2008 Max Walton

FFPR: Cost Functions Aspect Ratio Wirelength Computed as a penalty function Computes change in cost of the aspect ratio Wirelength Adds wirelength of each interconnect in design Half-perimeter bounding box is used for each interconnect Jun 12, 2008 Max Walton

FFPR: Cost Functions Congestion Cost Probability Congestion model 2D array of bins (CLBs in Virtex 4) A pin lies in only one bin A bin may contain multiple pins Sum of probabilites of all the paths that pass through bin Bin is congested if its congestion exceeds a threshold Calculated as sum of excess congestion of each bin Jun 12, 2008 Max Walton

FFPR: Cost Functions Reconfiguration Frames Cost Computed by looking at the fixed and reconfigurable regions compared with next design Consecutive design frames are added together to get total number Jun 12, 2008 Max Walton

FFPR: Moves Moves on Blocks Moves on Data Representation Changing orientation of a block Changing aspect ratio Changing whitespace along the border Moves on Data Representation Compaction: swapping random modules Compaction: moving block left/right or up/down Matching Jun 12, 2008 Max Walton

Moves: Changing the Whitespace Add four offsets to the blocks n, e, w, s Range {0 .. 5} Jun 12, 2008 Max Walton

FFPR: Matching 2 designs is equivalent to bipartite matching Matching for multiple designs Leads to many cases Jun 12, 2008 Max Walton

FFPR: Matching Jun 12, 2008 Max Walton

Results Matching: 50% savings on frames (50% partial matching) Jun 12, 2008 Max Walton

Results Direction of matching can impact design D1  D2 vs. D2  D1 Dependent Mode as much as 3X wirelength of combined/independent 50% higher on average Combined 9% more wirelength than independent Multilayer vs. traditional floorplanner 12% better clock period on average Reduces place and route time Jun 12, 2008 Max Walton

References “Multi-layer floorplanning for reconfigurable designs”, L. Singhal and E. Bozorgzadeh, IET Comput. Digit. Tech., 2007, 1, pp. 276-294 Jun 12, 2008 Max Walton

Project Create a Scatter Search implementation in Celoxica Handel-C Search out better performance from Handel-C version of SS Use Handel-C constructs to gain better performance Attempt multiple approaches of implementation (time permits) Jun 12, 2008 Max Walton

Project Status Used C code for 0-1 Knapsack Problem from “Scatter Search: Methodology and Implementations in C” by Laguna and Marti Currently converting to avoid pointer use and use less complex data structures more inherent in hardware Jun 12, 2008 Max Walton