EGR 2131 Unit 4 Combinational Circuits: Analysis & Design Read Mano & Ciletti, Sections 4.1 to 4.4. Homework #4 and Lab #4 due next week. Quiz next week. -Do Quiz #3. Handouts: Unit 4 Practice Sheets;

Combinational Versus Sequential A combinational logic circuit is a circuit whose output depends only on the circuit’s present inputs. (“Has no memory of the past.”) Covered in the book’s Chapter 4. A sequential logic circuit is a circuit whose output may depend on the circuit’s previous states as well as its present inputs. (“Has a memory.”) Covered in the book’s Chapter 5. Examples: Bell that rings if key in ignition and door open. Microwave panel that remembers keys pressed before START. 2

Feedback Paths The key to creating sequential circuits (ones that “have memory”) is to include feedback paths, which route the output from a gate back to the input of an earlier gate. Example of a circuit with a feedback path: 3

Components with Internal Feedback Paths We’ll see in Chapter 5 that components called latches and flip-flops have internal feedback paths. Here are logic symbols for some latches and flip-flops: Each of these boxes contains several interconnected gates with feedback paths. 4

How To Tell Whether a Circuit Is Combinational Or Sequential A circuit is sequential if its logic diagram contains feedback paths or contains sequential components such as latches or flip-flops. Otherwise it is combinational. So if the diagram just contains gates, and does not have any feedback paths, then the circuit is combinational. 5

Three Ways of Representing a Combinational Circuit Recall that we have at least three ways of describing a combinational logic circuit: Diagram showing the logic gates. Boolean expression. Truth table. Given any one of these, you should be able to write the other two. See examples on following slides.

From Gate Diagram to Boolean Expression or Truth Table Given a gate diagram, you should be able to: Write a Boolean expression for the diagram. Write the truth table for the diagram. Example: Write a Boolean expression and the truth table for the following gate diagram. -Do practice question 1.

From Boolean Expression to Gate Diagram or Truth Table Given a Boolean expression, you should be able to: Draw a gate diagram that implements the expression. Write the truth table for the expression. In many cases your job will be easier if you first use Boolean algebra or a Karnaugh map to simplify the expression. Example: Draw a gate diagram and write the truth table for X = A′B′ + ABC′ -Do practice question 2.

From Truth Table to Boolean Expression or Gate Diagram Given a truth table, you should be able to: Write a Boolean expression for that truth table. Here’s how: For each row in the truth table with a 1 in the output column, list the corresponding minterm. OR together all of the minterms from Step a. Draw a gate diagram that implements the truth table. Example: Write a Boolean expression and draw a gate diagram for the truth table on the next slide.

Example: From Truth Table to Boolean Expression or Gate Diagram C X 1 -Do practice question 3.

Analysis Versus Design On the previous slides we’ve been practicing what our book calls “Analysis of Combinational Circuits.” Analysis typically starts with a logic diagram and ends with a truth table or Boolean expression, and, possibly, a brief description in English of the circuit’s behavior (such as “This circuit’s output is HIGH if and only if a majority of its inputs are HIGH.”)

Analysis Versus Design (Cont’d.) The task of designing a combinational circuit reverses the order of the steps. We start with a verbal description of what the circuit is supposed to do, and we end up with a logic diagram of a circuit that does it.

“Classical” Design Procedure The next few slides deal with the “classical” design procedure, which means the way it had to be done before the advent of computer-based tools such as VHDL combined with Quartus II. With these new tools, designers don’t need to do as much classical design, but it’s still important for you to understand how to design a simple circuit the “old-fashioned way.”

Design Procedure The book identifies four (or five) steps: From the specifications, determine the number of inputs and outputs, and assign a symbol to each. Build a truth table showing the relationship between inputs and outputs. Use K-maps to find the simplified expression for each output as a function of the inputs. Draw the logic diagram. Verify that the resulting circuit performs as desired. The text combines my steps 4 and 5 as step 4.

Design Procedure: Example The book’s example: design a circuit that converts from BCD code to excess-3 code for the decimal digits.

Step 1. Determine Number of Inputs and Outputs From the problem statement, we can see that our circuit will need four inputs (one for each bit of the input BCD code) and four outputs (one for each bit of the output excess-3 code). Let’s call the four inputs A, B, C, D. And let’s call the four outputs w, x, y, z.

Step 2. Build a Truth Table For our current problem, this step is easy: Note that what we’ve really got here is four truth tables, one for each output.

Step 3. Find Simplified Expression for Each Output We’ll build a K-map for each output and read off the expression. Here it is for output w: -Do practice question 4.

Step 4. Draw the Logic Diagram From the Boolean expressions we can draw the gates: = A + B(C + D)

Step 5. Verify That It Works There are a few ways we can approach this verification step: Using the logic diagram, manually determine the value of each output for each possible combination of inputs. Build the circuit in Quartus and then simulate it. You’ll do this in Lab 4. Build the circuit in Quartus and then download it to the DE2-115 board and test it using switches and LEDs. You’ll also do this in Lab 4.

Title Add slides here on Sections 4.12, 4.13. ieee_standard data type Behavioral modeling versus entering Boolean equations or truth tables. AND gate as an example.

Two Ways to Simulate in Quartus II Recall that we use simulation to test a design’s operation “virtually” before we “burn” the design to a chip. There are at least two ways to simulate a design in Quartus II. Using a vector waveform file. This is the simpler but less sophisticated way to do it. Using a testbench. This is the more powerful but more complicated way to do it.

Two Ways to Simulate in Quartus II (Cont’d.) When using a vector waveform file, we graphically set up the input waveforms. When using a testbench, we write HDL code that describes the input waveforms. Using either approach, the simulator then generates output waveforms based on our input waveforms.

A Variety of Choices So we have several options for entering and simulating a design: Schematic entry + vector waveform simulation Sometimes we’ll do this. + Text entry + vector waveform simulation Sometimes we’ll do this. + Schematic entry + testbench simulation + Text entry + testbench simulation This is how the pros do it! +

VHDL Reserved Words for Simulation Of the 120 or so reserved words in VHDL, many are used for simulation only and are said to be non-synthesizable, which means Quartus ignores them when generating the code to be downloaded to a chip. An example is AFTER, which we saw earlier in the testbench fragment. Some reserved words, such as WAIT, may or may not be synthesizable, depending on how you use them.