Testing PCI Express Generation 1 & 2 with the RTO Oscilloscope Guido Schulze, Product Manager 1TDP Rev. 1.0, April 2017

Outline PCI Express technology overview R&S test solutions PCI Express 1.1/2.0 Trigger & Decode option PCI Express 1.1/2.0 Compliance test option March 2017 PCIe Gen 1&2 testing with R&S RTO oscilloscope

Market trends – PCI Express More data All around backbone processing: Big data, IoT as drivers for faster data lanes PCIe Gen4 Specification Lower speed generations in industrial applications: Powerful modular PC cards and respective adapter cards PCIe Gen1..3 Specifications March 2017 PCIe Gen 1&2 testing with R&S RTO oscilloscope

Technologie Overview PCI Express March 2017 PCIe Gen 1&2 testing with R&S RTO oscilloscope

PCI Express (PCIe) Industry standard for interconnection First release of PCIe 1.0 was in 2003 It replaces the PCI & PCI-X busses which where parallel interfaces PCIe is a serial link, simplest case is one 2,5 GT/s link, which give 250 MB/s transfer speed Serial interface was chosen because of lower I/O Pin count smaller physical size easier scalable Standardization is maintained and developed by the PCI Special Interest Group (PCI-SIG) consisting of more than 900 companies March 2017 PCIe Gen 1&2 testing with R&S RTO oscilloscope

PCI Express (PCIe) Terminology GT/s: Giga Transfer per second (since 8b/10b decode is used it is not equal to Giga Bit per second) 8b/10b: 8Bit / 10Bit encoding scheme, ensure DC-balance (long term ratio of transmitted “0” and “1” is 50%) which allow reliable clock recovery, on the cost of lower raw data transfer speed Interconnect / Link: Logical connection between PCI Express devices An Interconnect / Link can have 1/2/4/8/12/16/32 lanes Lane: Dual differential signal pair (one pair for receive, one pair for transmit), 4 wires per Lane Differential signal pair: Two unidirectional LVDS signals, March 2017 PCIe Gen 1&2 testing with R&S RTO oscilloscope

PCI Express (PCIe) Versions PCIe 1.x and 2.x are the most common versions PCIe 3.0 for high end applications (extra graphic speed, server) PCIe 4.0 standard is in the process of roll-out PCIe Version Transfer rate [GT/s] Funda-mental [GHz] 3rd harm. for T&D and Signal Integrity debug 5th harm. for compliance testing RTO coverage Trigger & Decode Compliance 1.x 2,5 1,25 3,75 6,25 RTO2044 RTO2064 2.x 5 7,5 12,5 (up to 2.5 GT/s) 3.0 8 4 12 20 4.0 16 24 40 March 2017 PCIe Gen 1&2 testing with R&S RTO oscilloscope

PCI Express (PCIe) terminology Tolopology CPU PCIe Root complex (Bus 0 – internal) PCIe endpoint Device Link (Bus 6) Frontside bus PCIe to xxx Bridge Link (Bus 5) Memory PCIe Switch (Bus 2) PCIe endpoint Device Memory bus Link (Bus 1) Link (Bus 3) Legacy endpoint Device Link (Bus 4) March 2017 PCIe Gen 1&2 testing with R&S RTO oscilloscope

PCI Express (PCIe) terminology Link Root complex (Bus 0 – internal) PCIe endpoint Device Link (Bus 6) Lane 1 Lane x (max. 32) March 2017 PCIe Gen 1&2 testing with R&S RTO oscilloscope

PCI Express (PCIe) Lane Root complex (Bus 0 – internal) PCIe endpoint Device Link (Bus 6) Lane 1 Channel 1 – differential pair Upstream Port (transmitter) Downstream Port (receiver) Downstream port (receiver) Upstream Port (transmitter) Channel 2 – differential pair Lane x (max. 32) March 2017 PCIe Gen 1&2 testing with R&S RTO oscilloscope

PCI Express (PCIe) Signaling Terminations on-die to 100 ohms differential (+/- 15%) AC Coupled Differential Pairs (LVDS) PCIe Gen1 – voltage max. 1,200 mV, typically 800 mV Clock is embedded Reference Clock March 2017 PCIe Gen 1&2 testing with R&S RTO oscilloscope

R&S Test Solution a) Trigger & Decode Option b) Compliance Test Option March 2017 PCIe Gen 1&2 testing with R&S RTO oscilloscope

RTO-K72 - PCI Express 1.1/2.0 Trigger & Decode Option At a Glance Full support up to 5 Gbit/s and x4 link size Predefined or user selectable bit rates Separately configurable CDR for decoding Reliable triggering on protocol detail such as Transaction Layer Packets (TLP), Data Layer Packets (DLLP), Ordered Sets and Errors Selectable decoding layer: bits, Scrambled or Descrambled 8b10b word, final protocol layer Powerful search capabilities Most compact debug solution with RTO2064 and RT-ZM60 probe March 2017 PCIe Gen 1&2 testing with R&S RTO oscilloscope

Decode Very easy setup Highlights: Customizable CDR Various decode layers March 2017 PCIe Gen 1&2 testing with R&S RTO oscilloscope

Decode Results Color coded protocol details Result table with overview and details March 2017 PCIe Gen 1&2 testing with R&S RTO oscilloscope

Trigger Comprehensive Search based SW-Trigger March 2017 PCIe Gen 1&2 testing with R&S RTO oscilloscope

PCI Express 1.1/2.0 Compliance Test Option At a Glance PCI Express 1.1/2.0 with data rate up to 2.5 Gbit/s Support of Add-in Card and System Motherboard Based on PCI-SIG Standard post-processing analysis software and test fixtures (CBB, CLB) Test of Signal Quality and Reference Clock Embedded in R&S®ScopeSuite Compliance Test application Step-by-step wizard for user guidance Clear and comprehensive test documentation Most compact debug solution with RTO2064 and RT-ZM60 probe March 2017 PCIe Gen 1&2 testing with R&S RTO oscilloscope

Supporte PCIe Compliance Tests March 2017 PCIe Gen 1&2 testing with R&S RTO oscilloscope

Further Debugging Capabilities Further debugging tools: Realtime mask testing (standard capability) Serial pattern trigger (standard capability) HW CDR (optional) Jitter analysis (optional) 2.5 Gbit/s 5.0 Gbit/s March 2017 PCIe Gen 1&2 testing with R&S RTO oscilloscope

Typical Product Configuration Typical developers tasks: Debugging the PCIe link on protocol and physical layer (SI) level Recommended configuration: RTO2064 oscilloscope 1..4x RT-ZM60 modular probes + RT-ZMA10 solder-in tip module RTO-K72 PCIe 1.1/2.0 T&D option RTO-K81 PCIe 1.1/2.0 Compliance test option PCI-SIG CBB/CLB test fixtures (https://pcisig.com/specifications/order-form) March 2017 PCIe Gen 1&2 testing with R&S RTO oscilloscope

Thank you.