1. Introduction to the Common Electrical Interface (CEI)
July 2006
Introduction to the Common Electrical Interface (CEI)
Graeme Boyd PMC-Sierra

2. Agenda What is CEI? Related OIF Interfaces or Protocols
CEI Electrical Interfaces
Some CEI Restrictions
CEI Compliance Strategy
CEI Futures

3. What is CEI? (1 of 5)
CEI
A faster electrical interface is required to provide higher density and/or lower cost interfaces for payloads of 10Gbps and higher, including SERDES to Framer Interface (SFI), System Packet Interface (SPI), TDM-Fabric to Framer Interface (TFI).
Electrical and jitter specifications for future interfaces including SFI, SPI and TFI for OIF as well as for other interfaces unrelated to OIF (examples could include Serial Rapid IO, SAS, Ethernet, etc). It does not contain any protocol implementations (that is contained within the OIF’s CEI-P document or within other standards).
Release 2.0 is available for free download at

4. What is CEI? (2 of 5) Jitter and interoperability Methodology
OIF-CEI-02.0 is the latest publicly available version which contains:
Jitter and interoperability Methodology
SxI-5, SFI-4.2, SFI-5.1, SPI-5.1 & TFI-5: Compliance information only (the real specifications can be found here)
CEI-6G-SR: Data lane(s) that support bit rates from to 6.375Gbps over a 20cm link on a PCB with up to one connector
CEI-6G-LR: Data lane(s) that support bit rates from to 6.375Gbps over a 1m link on a PCB with up to two connectors
CEI-11G-SR: Data lane(s) that support bit rates from 9.95 to 11.1Gbps over a 20cm link on a PCB with up to one connector
CEI-11G-MR: Data lane(s) that support bit rates from 9.95 to 11.1Gbps over a 60cm link on a PCB with up to two connectors
CEI-11G-LR: Data lane(s) that support bit rates from 9.95 to 11.1Gbps over a 1m link on a PCB with up to two connectors

5. What is CEI? (3 of 5)
CEI shall define the applicable data characteristics
e.g. DC balance, transition density, maximum run length
CEI shall define channel models and compliance points
CEI shall not:
Define the pin assignments or select a specific connector
Define a management interface
CEI shall allow both single and multi-lane applications
CEI shall support AC coupling & hot plug
CEI shall achieve a BER of better than per lane (with the test requirement of per lane)

6. What is CEI? (4 of 5)
Short & long reach links should interoperate under 20cm
CEI-11G-SR links shall be capable of supporting SONET/SDH compliance at the optical carrier (OC) interface
Also compatible with XFI links within the XFP specification
CEI-6G-LR links shall accommodate legacy IEEE XAUI and TFI-5 compliant backplanes.
The primary focus of the CEI-11G-LR links will be for non-legacy applications
Optimized for overall cost-effective system performance including total power dissipation

7. What is CEI? (5 of 5) SR: 0 – 20cm (6G & 11G) MR: 0 – 60cm (11G only)
LR: 0 – 1m (6G & 11G)
6G: – 6.375Gbps
11G: 9.95 – 11.10Gbps
Does specify
Channel Models Run Length
Compliance points Jitter
DC Balance BER
Transition Density Coupling
Interoperability Hot Plug
Does not specify
Lane Count Pinout
Connector Types Protocol
Management Interface
Power Supplies
Mechanical / Form Factor

8. Related OIF Interfaces or Protocols
SxI-5
Gbps electrical specification that uses the compliance part of CEI
SFI-4.2
A multi-lane Gps link that uses the compliance part of CEI
SFI-5.1
SPI-5.1
TFI-5
SFI-5.2 (In progress)
A multi-lane link that uses CEI-11G-SR
TDM-P (In progress)
A protocol that can be used on top of CEI-6G-LR (next generation TFI-5 link)
CEI-P
A protocol that can be used on top of CEI-6G or CEI-11G
SPI-S (In progress)
A multi-lane link that can be used on top of CEI-6G or CEI-11G
CEI-25G (In progress)
A 25G electrical link (once done will go into OIF-CEI-03.0)
SLA (Just starting)

9. Possible CEI Electrical Interfaces

10. Some CEI Restrictions (1 of 2)
Average transition density and average DC balance needs to converge to over a 30,000 bit period with a probability of at least one minus the BER ratio
Probability of run lengths over 10 to be proportional to 2-N for N-like bits in a row (N10). Hence, a run length of 40 bits would occur with a max probability of 2-40.
If a fixed block coding scheme is used (e.g. 8B/10B), the input data must be either be scrambled before coding or the coded data must be scrambled prior to transmission
This will prevent input data creating killer patterns (e.g. CJPAT patterns)

11. Some CEI Restrictions (2 of 2)
The ground difference between the driver and the receiver shall be within ±50mV for SR links and ±100mV for MR & LR links
Each connector is budgeted 50mV
Both driver and receiver lane-to-lane skew are each allowed up to 500ps. Higher protocol layers must allow for this additional (1ns) skew.
SR links have a standard open eye at the receiver, but for MR & LR links the eye maybe closed at the receiver hence requiring receiver equalization

12. CEI Compliance Strategy [1 of 3]
Rather than specifying materials, channel components, or configurations, the CEI specification focuses on effective channel characteristics
Hence a short length of poorer material should be equivalent to a longer length of premium material. A ‘length’ is effectively defined in terms of its attenuation rather than its physical length.
CEI compliance method defines:
Transmitter compliance in terms of eye masks, output jitter and certain emphasis abilities
Channel compliance uses worst case transmitter design and a “ideal reference receiver”
Receiver compliance must tolerate any compliant transmitter and channel

13. CEI Compliance Strategy [2 of 3]
For SR links CEI has chosen to specify the transmitter and receiver. This then implies what are compliment channels.
Similar to most other SERDES standards, except that CEI is using statistical eye’s (due to BER requirements). The Tx and channel compliance are done using a tool that OIF developed called StatEye.
Open Eye at
Rx pins
Eye plot curtsy of Molex

14. CEI Compliance Strategy [3 of 3]
As both MR and LR links can have a closed eye at the receiver, CEI has chosen to move the “receiver” spec point to after an “ideal receive equalizer”. Thus specifying the transmitter and compliment channels while implying the receiver spec.
So however the real receiver is implemented it needs to be equivalent or better than the “ideal reference equalizer”. The Tx and channel compliance are done using a tool that OIF developed called StatEye.
Eye completely closed at Rx pins
Open Eye after EQ
Eye plots curtsy of Molex

15. CEI Futures The OIF is currently working on updates for OIF-CEI-02.0
Editorial changes, clarifications, etc
The OIF is also working on new clauses (for example CEI-20G) for future links.

16. It is the mission of the OIF to support the industry by sharing the results of its efforts with other organizations.

17. Thank You!