ALU Architecture and ISA Extensions Lecture notes from MKP, H. H. Lee and S. Yalamanchili

Reading Sections 3.2-3.5 (only those elements covered in class) Appendix B.5 Practice Problems: 26, 27 Goal: Understand the ISA view of the core microarchitecture Time, space, energy Organization of functional units and register files into basic data path blocks

Overview Instruction Set Architectures have a purpose Applications dictate what we need We only have a fixed number of bits Impact on accuracy More is not better We cannot afford everything we want Basic Arithmetic Logic Unit (ALU) Design Addition/subtraction, multiplication, division

Reminder: ISA Who sees what? 0x00 0x01 0x02 0x03 0x1F 0xFFFFFFFF byte addressed memory Register File (Programmer Visible State) Memory Interface stack 0x00 0x01 0x02 0x03 Processor Internal Buses 0x1F Dynamic Data Data segment (static) Text Segment Programmer Invisible State Reserved 0xFFFFFFFF Program Counter Instruction register Arithmetic Logic Unit (ALU) Memory Map Kernel registers Who sees what?

Arithmetic for Computers Morgan Kaufmann Publishers 17 February, 2018 Arithmetic for Computers Operations on integers Addition and subtraction Multiplication and division Dealing with overflow Operation on floating-point real numbers Representation and operations Let us first look at integers Chapter 3 — Arithmetic for Computers

Morgan Kaufmann Publishers 17 February, 2018 Integer Addition(3.2) Example: 7 + 6 Overflow if result out of range Adding +ve and –ve operands, no overflow Adding two +ve operands Overflow if result sign is 1 Adding two –ve operands Overflow if result sign is 0 Chapter 3 — Arithmetic for Computers

Morgan Kaufmann Publishers 17 February, 2018 Integer Subtraction Add negation of second operand Example: 7 – 6 = 7 + (–6) +7: 0000 0000 … 0000 0111 –6: 1111 1111 … 1111 1010 +1: 0000 0000 … 0000 0001 Overflow if result out of range Subtracting two +ve or two –ve operands, no overflow Subtracting +ve from –ve operand Overflow if result sign is 0 Subtracting –ve from +ve operand Overflow if result sign is 1 2’s complement representation Chapter 3 — Arithmetic for Computers

Morgan Kaufmann Publishers 17 February, 2018 ISA Impact Some languages (e.g., C) ignore overflow Use MIPS addu, addui, subu instructions Other languages (e.g., Ada, Fortran) require raising an exception Use MIPS add, addi, sub instructions On overflow, invoke exception handler Save PC in exception program counter (EPC) register Jump to predefined handler address mfc0 (move from coprocessor register) instruction can retrieve EPC value, to return after corrective action (more later) ALU Design leads to many solutions. We look at one simple example Chapter 3 — Arithmetic for Computers

ISA View Register-to-Register data path CPU/Core $0 $1 $31 ALU Register-to-Register data path We want this to be as fast as possible

Multiplication (3.3) Long multiplication 1000 × 1001 0000 1001000 multiplicand 1000 × 1001 0000 1001000 multiplier product Length of product is the sum of operand lengths

Morgan Kaufmann Publishers 17 February, 2018 A Multiplier Uses multiple adders Cost/performance tradeoff Can be pipelined Several multiplication performed in parallel Chapter 3 — Arithmetic for Computers

Morgan Kaufmann Publishers 17 February, 2018 Division(3.4) Check for 0 divisor Long division approach If divisor ≤ dividend bits 1 bit in quotient, subtract Otherwise 0 bit in quotient, bring down next dividend bit Restoring division Do the subtract, and if remainder goes < 0, add divisor back Signed division Divide using absolute values Adjust sign of quotient and remainder as required quotient dividend 1001 1000 1001010 -1000 10 101 1010 divisor remainder n-bit operands yield n-bit quotient and remainder Chapter 3 — Arithmetic for Computers

Morgan Kaufmann Publishers 17 February, 2018 Faster Division Can’t use parallel hardware as in multiplier Subtraction is conditional on sign of remainder Faster dividers (e.g. SRT division) generate multiple quotient bits per step Still require multiple steps Customized implementations for high performance, e.g., supercomputers Chapter 3 — Arithmetic for Computers

ISA View Additional function units and registers (Hi/Lo) CPU/Core $0 $1 $31 ALU Multiply Divide Hi Lo Additional function units and registers (Hi/Lo) Additional instructions to move data to/from these registers mfhi, mflo What other instructions would you add? Cost?

Morgan Kaufmann Publishers 17 February, 2018 Floating Point(3.5) Representation for non-integral numbers Including very small and very large numbers Like scientific notation –2.34 × 1056 +0.002 × 10–4 +987.02 × 109 In binary ±1.xxxxxxx2 × 2yyyy Types float and double in C normalized not normalized Chapter 3 — Arithmetic for Computers

IEEE 754 Floating-point Representation Single Precision (32-bit) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 S exponent significand 1bit 8 bits 23 bits (–1)sign x (1+fraction) x 2exponent-127 Double Precision (64-bit) 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 S exponent significand 1bit 11 bits 20 bits significand (continued) 32 bits (–1)sign x (1+fraction) x 2exponent-1023

Floating Point Standard Morgan Kaufmann Publishers 17 February, 2018 Floating Point Standard Defined by IEEE Std 754-1985 Developed in response to divergence of representations Portability issues for scientific code Now almost universally adopted Two representations Single precision (32-bit) Double precision (64-bit) Chapter 3 — Arithmetic for Computers

Morgan Kaufmann Publishers 17 February, 2018 FP Adder Hardware Much more complex than integer adder Doing it in one clock cycle would take too long Much longer than integer operations Slower clock would penalize all instructions FP adder usually takes several cycles Can be pipelined Example: FP Addition Chapter 3 — Arithmetic for Computers

Morgan Kaufmann Publishers 17 February, 2018 FP Adder Hardware Step 1 Step 2 Step 3 Step 4 Chapter 3 — Arithmetic for Computers

FP Arithmetic Hardware Morgan Kaufmann Publishers 17 February, 2018 FP Arithmetic Hardware FP multiplier is of similar complexity to FP adder But uses a multiplier for significands instead of an adder FP arithmetic hardware usually does Addition, subtraction, multiplication, division, reciprocal, square-root FP  integer conversion Operations usually takes several cycles Can be pipelined Chapter 3 — Arithmetic for Computers

Morgan Kaufmann Publishers 17 February, 2018 ISA Impact FP hardware is coprocessor 1 Adjunct processor that extends the ISA Separate FP registers 32 single-precision: $f0, $f1, … $f31 Paired for double-precision: $f0/$f1, $f2/$f3, … Release 2 of MIPs ISA supports 32 × 64-bit FP reg’s FP instructions operate only on FP registers Programs generally do not perform integer ops on FP data, or vice versa More registers with minimal code-size impact Chapter 3 — Arithmetic for Computers

ISA View: The Co-Processor ALU Hi Multiply Divide Lo $0 $1 $31 FP ALU BadVaddr Status Causes EPC CPU/Core Co-Processor 1 Co-Processor 0 later Floating point operations access a separate set of 32-bit registers Pairs of 32-bit registers are used for double precision

Morgan Kaufmann Publishers 17 February, 2018 Associativity Floating point arithmetic is not commutative Parallel programs may interleave operations in unexpected orders Assumptions of associativity may fail Need to validate parallel programs under varying degrees of parallelism Chapter 3 — Arithmetic for Computers

Performance Issues Latency of instructions Integer instructions can take a single cycle Floating point instructions can take multiple cycles Some (FP Divide) can take hundreds of cycles What about energy (we will get to that shortly) What other instructions would you like in hardware? Would some applications change your mind? How do you decide whether to add new instructions?

Domain Impact on the ISA: Example Scientific Computing Embedded Systems Integers Lower precision Streaming data Security support Energy constrained Floats Double precision Massive data Power constrained

Summary ISAs support operations required of application domains Note the differences between embedded and supercomputers! Signed, unsigned, FP, etc. Bounded precision effects Software must be careful how hardware used e.g., associativity Need standards to promote portability Avoid “kitchen sink” designs There is no free lunch Impact on speed and energy  we will get to this later

Study Guide Perform 2’s complement addition and subtraction (review) Add a few more instructions to the simple ALU Add an XOR instruction Add an instruction that returns the max of its inputs Make sure all control signals are accounted for Convert real numbers to single precision floating point (review) and extract the value from an encoded single precision number (review) Execute the programs (class website) that use floating point numbers. Study the memory/register contents via single step execution

Study Guide (cont.) Write a few simple programs for Multiplication/division of signed and unsigned numbers Use numbers that produce >32-bit results Move to/from HI and LO registers ( find the instructions for doing so) Addition/subtraction of floating point numbers Try to write a simple program that demonstrates that floating point operations are not associative (this takes some thought and review of the range of floating point numbers)

Glossary Co-processor Instruction set extensions Overflow Precision Signed arithmetic support Unsigned arithmetic support

Backup

Integer ALU (arithmetic logic unit)(B.5) Build a 1 bit ALU, and use 32 of them (bit-slice) operation result op a b res a b

Single Bit ALU Implements only AND and OR operations Operation Result Result A 1 B

Adding Functionality We can add additional operators (to a point) How about addition? Review full adders from digital design cout = ab + acin + bcin sum = a  b  cin

Building a 32-bit ALU

Subtraction (a – b) ? Two's complement approach: just negate b and add 1. How do we negate? A clever solution: sub B i n v e r t b 3 1 2 R s u l a C y I O p o A L U

Tailoring the ALU to the MIPS Need to support the set-on-less-than instruction(slt) remember: slt is an arithmetic instruction produces a 1 if rs < rt and 0 otherwise use subtraction: (a-b) < 0 implies a < b Need to support test for equality (beq $t5, $t6, $t7) use subtraction: (a-b) = 0 implies a = b

What Result31 is when (a-b)<0? 3 R e s u l t O p r a i o n 1 C y I B v b 2 L Unsigned vs. signed support

Test for equality Notice control lines: 000 = and 001 = or 010 = add 110 = subtract 111 = slt Note: zero is a 1 when the result is zero! Note test for overflow!