1. Arithmetic for Computers Chapter 3 1

2. Arithmetic for Computers  Operations on integers  Addition and subtraction  Multiplication and division  Dealing with overflow  Floating-point real numbers  Representation and operations §3.1 Introduction 2

3. Integer Addition  Example: 7 + 6 §3.2 Addition and Subtraction Overflow if result out of range Adding +ve and –ve operands, no overflow Adding two +ve operands Overflow if result sign is 1 Adding two –ve operands Overflow if result sign is 0 3

4. Integer Subtraction  Add negation of second operand  Example: 7 – 6 = 7 + (–6) +7:0000 0000 … 0000 0111 –6:1111 1111 … 1111 1010 +1:0000 0000 … 0000 0001  Overflow if result out of range  Subtracting two +ve or two –ve operands, no overflow  Subtracting +ve from –ve operand  Overflow if result sign is 0  Subtracting –ve from +ve operand  Overflow if result sign is 1 4

5. Arithmetic for Multimedia  Graphics and media processing operates on vectors of 8-bit and 16-bit data  Use 64-bit adder, with partitioned carry chain  Operate on 8×8-bit, 4×16-bit, or 2×32-bit vectors  SIMD (single-instruction, multiple-data)  Saturating operations  On overflow, result is largest representable value (positive or negative)  c.f. 2s-complement modulo arithmetic  E.g., clipping in audio, saturation in video 5

6. Multiplication  Start with long-multiplication approach 1000 × 1001 1000 0000 1000 1001000 Length of product is the sum of operand lengths multiplicand multiplier product §3.3 Multiplication 6

7. Multiplication Hardware Initially 0 7

8. Optimized Multiplier  Algorithm and hardware refined to take one clock cycle per step  Perform steps in parallel: add/shift One cycle per partial-product addition That’s ok, if frequency of multiplications is low The hardware is usually further optimized to halve the width of the adder and registers by noticing where there are unused portions of registers and adders 8

9.  Using 4-bit numbers to save space, multiply 2 ten × 3 ten, or 0010 two × 0011 two Multiplication - example 9

10. Faster Multiplier  Uses multiple adders  Cost/performance tradeoff Can be pipelined Several multiplication performed in parallel 10

11. LEGv8 Multiplication  Three multiply instructions:  MUL: multiply  Gives the lower 64 bits of the product  SMULH: signed multiply high  Gives the upper 64 bits of the product, assuming the operands are signed  UMULH: unsigned multiply high  Gives the lower 64 bits of the product, assuming the operands are unsigned 11

12. Division  Check for 0 divisor  Long division approach  If divisor ≤ dividend bits  1 bit in quotient, subtract  Otherwise  0 bit in quotient, bring down next dividend bit  Restoring division  Do the subtract, and if remainder goes < 0, add divisor back  Signed division  Divide using absolute values  Adjust sign of quotient and remainder as required 1001 1000 1001010 -1000 10 101 1010 -1000 10 n-bit operands yield n-bit quotient and remainder quotient dividend remainder divisor §3.4 Division 12

13. Division Hardware Initially dividend Initially divisor in left half 13

14.  Using a 4-bit version of the algorithm, divide 7 ten by 2 ten, or 0000 0111 two by 0010 two. Divide - example 14

15. Optimized Divider  One cycle per partial-remainder subtraction  The speed-up comes from shifting the operands and the quotient simultaneously with the subtraction.  This refinement halves the width of the adder and registers  Looks a lot like a multiplier!  Same hardware can be used for both 15

16.  Remember the signs of the divisor and dividend and then negate the quotient if the signs disagree -7  +2: quotient = -3  Remainder = (dividend – quotient x divisor) = -7 – (-3 x +2) = -1 -7  +2: quotient = -3, remainder = -1 +7  -2: quotient = -3, remainder = +1 -7  -2: quotient = +3, remainder = -1  The correctly signed division algorithm negates the quotient if the signs of the operands are opposite and makes the sign of the nonzero remainder match the dividend Signed Division 16

17. Faster Division  Can’t use parallel hardware as in multiplier  Subtraction is conditional on sign of remainder  Faster dividers (e.g. SRT division) generate multiple quotient bits per step using a table lookup based on the upper bits of the dividend and remainder  Still require multiple steps  The accuracy of this fast method depends on having proper values in the lookup table 17

18. LEGv8 Division  Two instructions:  SDIV (signed)  UDIV (unsigned)  Both instructions ignore overflow and division-by-zero  LEGv8 software must check the divisor to discover division by 0 as well as overflow. 18

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20. Floating Point  Representation for non-integral numbers  Including very small and very large numbers  Like scientific notation  –2.34 × 10 56  +0.002 × 10 –4  +987.02 × 10 9  Normalized number: A number in floating-point notation that has no leading 0s  In binary  ±1.xxxxxxx 2 × 2 yyyy  Types float and double in C  Floating point: Computer arithmetic that represents numbers in which the binary point is not fixed normalized not normalized §3.5 Floating Point 20