Piero Belforte, HDT 1997, THRIS (Telecom Hardware Robustness Inspection System) Project as CSELT-HDT cooperation: Achieving global hardware robustness in electronic systems.

Slides:



Advertisements
Similar presentations
Safety for electronic systems High-frequency Filtering of DC Power Lines Technical, constructional and practical issues with filtering on dc power lines.
Advertisements

ELECTROMAGNETIC COMPATIBILITY Dr. Donald Church Senior Staff Engineer International Rectifier Automotive Systems November 17, 2005.
SWITCH-MODE POWER SUPPLIES AND SYSTEMS Silesian University of Technology Faculty of Automatic Control, Electronics and Computer Sciences Ryszard Siurek.
A guide to Real Power Protection
CHAPTER 3: SPECIAL PURPOSE OP-AMP CIRCUITS
Analog Basics Workshop RFI/EMI Rejection
1CADENCE DESIGN SYSTEMS, INC. Using Allegro PCB SI to Analyze a Board’s Power Delivery System from Power Source to Die Pad International Cadence Usergroup.
Designing a EMC Compatible Electronic Meter using AD7755 a.
Fault Injection in Mixed-Signal Environment Using Behavioral Fault Modeling in Verilog-A Seyed‌ Nematollah Ahmadian, Seyed Ghassem Miremadi Behavioral.
EMC Models.
Event Detectors Interconnect Reliability Testing by Dr. John W. Sofia Analysis Tech Phone: (781) Fax: (781)
Loran Integrity Performance Panel Integrity Fault Tree for Loran Sherman Lo Second LORIPP Meeting Portland, OR September 23-24, 2002.
AP-EMC in Singapore MAY 19-22, 2008 – - IC-EMC a Demonstration Freeware for Predicting Electromagnetic.
Revised: Aug 1, EE4390 Microprocessors Lessons 29, 30 Welcome to the Real World!
공과대학 > IT 공학부 Embedded Processor Design Chapter 8: Test EMBEDDED SYSTEM DESIGN 공과대학 > IT 공학부 Embedded Processor Design Presenter: Yvette E. Gelogo Professor:
Buck Regulator Architectures
POWER PLANT USED IN TELECOM
1 4. EMC measurement methods. 2 Why EMC standard measurement methods Check EMC compliance of ICs, equipments and systems Comparison of EMC performances.
Research on Analysis and Physical Synthesis Chung-Kuan Cheng CSE Department UC San Diego
Origin of Emission and Susceptibility in ICs
MICAS Department of Electrical Engineering (ESAT) Design-In for EMC on digital circuit October 27th, 2005 AID–EMC: Low Emission Digital Circuit Design.
MICAS Department of Electrical Engineering (ESAT) Design-In for EMC on digital circuit December 5th, 2005 Low Emission Digital Circuit Design Junfeng Zhou.
ECG Monitor Objective o Provide users an economical ECG monitoring device o Raise awareness to the importance of a healthy heart and living o Allow doctors.
Electromagnetic Compatibility Test for CMS Experiment. Authors C. Rivetta– Fermilab F. Arteche, F. Szoncso, - CERN.
Etienne CARLIER, LBDS Audit, 28/01/2008 LBDS Environmental Aspects EMC, radiation, UPS… Etienne CARLIER AB/BT/EC.
Acquisition Crate Design BI Technical Board 26 August 2011 Beam Loss Monitoring Section William Vigano’ 26 August
Over View of CENELC Standards for Signalling Applications
Interactive Control in Engineering Projects Electronics and Control.
Very-Near-Field Solutions to Far-Field EMC Problems EMxpert Pre-Compliance EMC Testing Advanced Embedded Systems September 09, 2015.
System implementation of a power distribution scheme based on DC-DC converters F.Faccio, G.Blanchot, S.Michelis, C.Fuentes, B.Allongue, S.Orlandi CERN.
Pixel power R&D in Spain F. Arteche Phase II days Phase 2 pixel electronics meeting CERN - May 2015.
Tim Cunnyngham 2001 Future Energy Challenge Project
BRAIN TISSUE IMPEDANCE ESTIMATION Improve the Brain’s Evoked Potential’s source Temporal and Spatial Inverse Problem Improve the Brain Tissue Impedance.
Dr.F. Arteche EMC DEPFET Project: A general overview.
F. Arteche EMC: Electronics system integration for HEP experiments (Grounding & Shielding)
Reliability and Performance of the SNS Machine Protection System Doug Curry 2013.
Piero Belforte, HDT High Design Technology presentation by Alessandro Arnulfo (1999).
Piero Belforte, HDT Signal Integrity & EMC
Piero Belforte, 1999 H.D.T. Italia S.r.l. PRESENTATION Emmanuel LEROUX Chief Application Engineer.
Piero Belforte, HDT 1999: MULTIBOARD SIMULATION Emmanuel LEROUX Chief Application Engineer.
Piero Belforte, HDT: PRESTO Post-layout Rapid Exhaustive Simulation and Test of Operation.
Piero Belforte, HDT GENERAL OVERVIEW by Emmanuel LEROUX Chief Application Engineer 1999.
Piero Belforte, CSELT 1999: AEI_EMC_, EMC basics by Flavio Maggioni.
Piero Belforte, HDT 1999: PRESTO POWER by Alessandro Arnulfo.
High Speed Properties of Digital Gates, Copyright F. Canavero, R. Fantino Licensed to HDT - High Design Technology
Piero Belforte, HDT 1999: Modeling for EMC and High Frequency Devices, DAC 1999,New Orleans USA.
Piero Belforte, HDT 1998: Advanced Simulation and Modeling for Electronic System Hardware Design Part1 .
Piero Belforte, HDT 1998: Advanced Simulation and Modeling for Electronic System Hardware Design Part2 .
Piero Belforte, HDT, April 14, 2000, RISIP Project Radiated Immunity Simulation for Industrial Processes by Mariateresa Cosso.
Piero Belforte, HDT, MERITA project 2000: objectives, activities and results by Carla GIACHINO .
Piero Belforte, HDT, April 14, 2000 RISIP: Radiated Immunity 3-D Simulation for Industrial Processes 1 RISIP methodologies and software solutions.
Piero Belforte, HDT, July 2000: MERITA Methodology to Evaluate Radiation in Information Technology Application, methodologies and software solutions by Carla Giachino,
Piero Belforte 1997: Telecom Hardware Robustness Inspection System as CSELT WEB page.
Piero Belforte, CSELT/HDT, 1998: PCB RADIATED EMISSION PREDICTION AND VALIDATION
Piero Belforte 2010 : WE WERE PIONEERS, EARLY APPLICATIONS OF DIGITAL WAVE SIMULATORS (CSELT,YEARS 70s)
Presented by Under the esteemed guidance of D.GANGADHAR REDDY, M. Tech. Asst. Prof., EEE Department UNIVERSAL COLLEGE OF ENGINEERING & TECHNOLOGY AUTO.
Silicon Valley Test Conference 2013
IEEE NPEC SC2 Equipment Qualification Electromagnetic Compatibility Compliance Type Test-Design Considerations- Installation and Mitigation Standard/Guidance.
Business Processes Organization and Roles
Electric Field and Waves Instrument (EFW)
ETD/Online Report D. Breton, U. Marconi, S. Luitz
Open Book, Open Note 3-4 Multipart Questions
Unit 1B Shaker Table Testing.
Martin Shaw – Reliability Solutions
EMC problems of DSOI device and circuits
Open book, open notes, bring a calculator
I Alexander Nass for the JEDI collaboration
Integrated tool set for electro-thermal evaluation of ICs
Fault Tolerant Systems in a Space Environment
Presentation transcript:

Telecom Hardware Robustness Inspection System Key issue: Achieving global hardware robustness in electronic apparatus

Hardware design phase - signal integrity optimization (ringing, crosstalk, ground bounce, power supply distribution analysis), timing problem control - filtering/shielding optimization (EMI simulations) - reliability evaluation (components, architectural conceps, thermal analysis) Hardware/Software Integration phase - fault insertion, noise injection, experimental EMI precompliance tests EMC qualification phase - emission/susceptibility conformity tests Overall Fault Tolerance Verification phase - fault insertion Installation phase - environment interaction evaluation (grounding, shielding, EMI tests ) Hardware Robustness: a life-cycle issue

THRIS: CSELT/HDT partnership SI XTALK SSN What-If SPRINT PRESTO Faults/noise injection Conducted Radiated ESD Burst _SI_FI_EMC Close field measurements (EASYSCAN, NFA) Precompliance EMC (measurements near field) Conducted noise injection (RFI) EMC prediction Reliability RAP THRIS Physical tests on actual systems Data preparation require simulation performed with Presto

THRIS basic functionalities Common database (data extracted at design phase are the same used in EMC prediction and qualification (Fault insertion) Signal integrity prediction EMI prediction (radiated/conducted emission,conducted susceptibility) EMI performance optimization (What-If analysis) Reliability evaluation (RAPSODIA, METRICA) Fault injection (pin forcing technique) Noise injection Electrical/thermal monitoring EMI precompliance analysis (near-field, common mode currents, conducted susceptibility)

THRIS_FI: Pin forcing Mbit/s output streams Mbit/s input streams Fault Stage A Stage B Stage C Description: 3 Boards + backplane Mbit/s streams 6 16x16 switching matrices THRIS simulation model: circuit elements nodes timepoints 20’ simulation time on typ. ws.

Normal operation 5mA current injection 12mA current injection ecl interconnection N output testpoint THRIS_FI: Noise injection

THRIS new development Mainly in EMC field of application: Simulation: common mode, maximum radiation evaluation, close field maps in EASYSCAN Measure: generalized radio frequency noise injection