1. Razvan A. Ene High Design Technology - Italy DAC 1999 - New Orleans - USA Modeling for EMC and High Frequency Devices 1

2. High Design Technology 2

3. What degree of accuracy of the models is needed in order to correctly simulate the signals and the radiated electromagnetic field of PCBs? A way of avoiding such precise description using IBIS models is foreseen. Motivation 3

4. High Design Technology Why predict S.I. and e.m. emissions? Device modeling and related problems Electrical modeling for EMC Comparison with measurements Conclusions about S.I. and EMC simulation Improving IBIS Topics of Discussion 4

5. High Design Technology Considering S.I. & EMC aspects in PCBs only through compliance tests on the first prototype raises some problems completion date costs Solution: Predict wave forms & radiated emission at the design stage using post-layout simulation Why predict S.I. & e.m. emission? 5

6. High Design Technology Elements of an IBIS Model 6

7. High Design Technology Device modeling (for S.I.) SUBCKT name 1 2 10 20 COUT 2 0 value RSWVCC 7 2 1 0 PWL(0V 1E6 1V 0 2V 0) C=2P PVCC 7 8 1_static_char C=2P E1 8 9 1 0 dtf stf 0.1NS VCOMP 10 91 DC(5) Bvcc 91 9 dtf2 RSWGND 17 2 1 0 PWL(-1V 0 0V 0 1V 1E6) C=2P PGND 17 18 0_static_char C=2P Bgnd 99 19 dtf2 TD 99 20 C=6P.ENDS name 7

8. High Design Technology Device modeling (for S.I.) name is the name of the electrical model value is the value of the output capacitance 0_static_char is the static characteristic of the output at "0" logic level 1_static_char is the static characteristic of the ouput at "1" logic level 8

9. High Design Technology Device modeling (for S.I.) stf is the static transfer function of the output dtf is the dynamic transfer function of the output dtf2 is the dynamic transfer function of the clamping diode 9

10. High Design Technology Measuring the D.T.F.of the output impedance The bias probe is used to setup the bias condition at the DUT pin. It can be a simple 10k  1/8W resistor or a series of a 3.3mH inductor and a 330  1W resistor (the inductor on the DUT side). The purely resistive probe can be used for biasing CMOS input stages, because no biasing current is required. The RL probe is needed to bias output stages or input clamping diodes, that require a current source or sink at DUT pin. 10

11. High Design Technology Actual TDR responses of the AC74 input in clamping condition for two foundries 11

12. High Design Technology Simulated response of an inter- connection between two AC74 Only the dynamic response of the ground protection diode is different in the simulations A and B 12

13. High Design Technology Identifying the problem 13

14. High Design Technology Silicon implementation Concentrated vs. distributed clamp diodes small inductive effectlarge inductive effect dedicated clamp diodedistributed protection diode fast clampingslow clamping over shoot 14

15. High Design Technology Simulation vs. measures at 155Mb/s Comparison between simulation and measures of high- speed multiboard system (155Mbit/s) * 50000 elements * 32 simultaneous input sequence * 16000 time points * 25 min. simulation time ( SUN Ultra 1) 15

16. High Design Technology Important factors physical layout on the die spreading of the parameters accurate problem description adequate modeling of the problem high precision instrumentation 16

17. High Design Technology Some equivalences wide band models = accurate time domain characterisation (depends on your simulation engine) accurate simulation of the waveforms = accurate model of the components actualy mounted on the PCB Wasn’t all about design phase? 17

18. High Design Technology EMC measurement setup Semi-anechoical room at Lille University Measurements in far field The geometry: 18

19. High Design Technology Test case PCB with one microstrip 10 MHz CMOS oscillator 19

20. High Design Technology Problems Predicted e.m. field is very different from the measurements although we used: Accurate models for vias, pins and microstrip Special precautions in order to ensure lack of parasitic effects Green transfer function Driver model 20

21. High Design Technology Electrical modeling for EMC modify dtf in the device model in IBIS is given as a slope Measure dtf using a good probe (with low parasitic parameters) insert a dtf block instead of C out in the model Measure it using a Time Domain Reflectometer (TDR) 21

22. High Design Technology Electrical modeling for EMC Measuring dtf 22

23. High Design Technology Frequency spectrum of the signals 23

24. High Design Technology Signals on the trace 24

25. High Design Technology EMC spectrums IMPORTANT OBSERVATION: Although is a low speed circuit, EMC simulation requires a model valid until VERY HIGH frequencies 2 5

26. High Design Technology Conclusions Good agreement with measurement is obtained using appropriate models and simulation techniques The algorithm and modeling techniques are thus validated The aim of the designer is to keep the radiated fields under the standards, i.e. a worst case analysis 26

27. High Design Technology Conclusions During design phase is not realistic to measure each component (remember also the spread in the components characteristics) Make use in an appropriate mode of the typical, min. and max. values in IBIS model (EMC compliance = Signal Integrity = Timing Simulation) 27

28. High Design Technology Advises for a successful designer have fully knowledge of the advantages and limitations of your simulation engine have clear ideas about what simulation can give, and what practical use one can make of the results make appropriate choice of the model parameters (it is more usefull having the spreading rather than a single measurement) 28

29. High Design Technology Improving IBIS fill in all min. / max. fields introduce a field that, for critical parameters like C out, gives the statistical distribution of the values spreading revive the Rise and Fall waveform voices, in order to handle corectly the waveforms of the open output 29

30. High Design Technology Improving IBIS introduce supplementary fields in order to support the TDR measurements of the dynamic behaviour of the output impedance in both normal and clamping condition (high and low level); in this way even far more complex problems can be addressed 30