Digital Logic & Design Dr. Waseem Ikram Lecture No. 25

J-K flip-flop with Asynchronous Preset and Clear inputs

Logic Symbol of a J-K flip-flop with Asynchronous inputs

InputOutput Q t+1 00Invalid Clocked operation PRE CLR Truth table of J-K flip-flop with Asynchronous inputs

Timing diagram of a J-K flip-flop with Preset and Clear inputs

Master-Slave flip-flop

InputOutpu t CLKJKQ t+1 Pulse00QtQt Truth table of the Master-Slave J- K flip-flop t Q

Timing diagram of a Master Slave J-K flip- flop

Propagation Delay, clock to low-to-high transition of the output

Propagation Delay, clock to high- to-low transition of the output

Propagation Delay, preset to low- to-high transition of the output

Set-up time for a D flip-flop

Propagation Delay, clear to high-to-low transition of the output

Hold time for a D flip-flop

Circuit diagram of a One-Shot

Timing diagram of a One-Shot

Timing diagram of a non retriggerable One-Shot Trigger Output of One-Shot t 1 t 2 t 3 t 4 t 5 t 6

Timing diagram of a non- retriggerable One-Shot with ignored triggers Trigger Output of One-Shot t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 10

Recap D flip-flop applications Data Storage Synchronizing Asynchronous Inputs Parallel data Transfer J-K flip-flop J-K flip-flop applications Sequence Detector Frequency Divider Shift Register Counter

Asynchronous Inputs J-K flip-flop with asynch. inputs (fig 1a) Logic symbol asynch. J-K flip-flop (fig 1b) Function table (tab1) Timing diagram (fig 1c)

Master-Slave flip-flop Master Slave flip-flop (fig 2a) Function table (tab 2) Timing diagram (fig 2b)

Operating Conditions Flip-Flop Operating Conditions Propagation delay (fig 3,4,5,6) Set-up time (fig 7) Hold Time (fig 8) Max clock frequency Pulse Width Power Dissipation

Multivibrators Mono-Stable Multi-vibrator (fig 9) Non-Retriggerable (fig 10) Retriggerable (fig 11)