1 Models for Hand Analysis NMOS Transistor PMOS Transistor V DSN  V GSN -V TN V DSN  V GSN -V TN V DSP  V GSP -V TP V DSP  V GSP -V TP K N =(W/L)K’

Slides:

Advertisements

Similar presentations

MICROWAVE FET Microwave FET : operates in the microwave frequencies

Advertisements

MODULE SYSTEM LOGIC GATE CIRCUIT DQ CMOS Inverter ASIC Full-Custom Semi-Custom Programmable FPGA PLD Cell-Based Gate Arrays General Purpose DRAM & SRAM.

(Neil weste p: ).  A MOS transistor is a majority-carrier device, in which the current in a conducting channel between the source and the drain.

Digital Integrated Circuits© Prentice Hall 1995 Devices Jan M. Rabaey The Devices.

VLSI Design/ RMC© D. Al-Khalili Devices-2 1 The Threshold Voltage  The voltage applied between the gate and the source which causes the beginning of the.

Introduction to CMOS VLSI Design Lecture 3: CMOS Transistor Theory David Harris Harvey Mudd College Spring 2004.

Introduction to CMOS VLSI Design Lecture 5 CMOS Transistor Theory

VLSI Design CMOS Transistor Theory. EE 447 VLSI Design 3: CMOS Transistor Theory2 Outline Introduction MOS Capacitor nMOS I-V Characteristics pMOS I-V.

Introduction to VLSI Circuits and Systems, NCUT 2007 Chapter 6 Electrical Characteristic of MOSFETs Introduction to VLSI Circuits and Systems 積體電路概論賴秉樑.

EE415 VLSI Design The Devices: MOS Transistor [Adapted from Rabaey’s Digital Integrated Circuits, ©2002, J. Rabaey et al.]

Lecture #16 OUTLINE Diode analysis and applications continued

Introduction to CMOS VLSI Design Lecture 3: CMOS Transistor Theory

Week 8b OUTLINE Using pn-diodes to isolate transistors in an IC

Lecture 2: CMOS Transistor Theory

VLSI design Lecture 1: MOS Transistor Theory. CMOS VLSI Design3: CMOS Transistor TheorySlide 2 Outline  Introduction  MOS Capacitor  nMOS I-V Characteristics.

ECE 431 Digital Circuit Design Chapter 3 MOS Transistor (MOSFET) (slides 2: key Notes) Lecture given by Qiliang Li 1.

Lecture 3: CMOS Transistor Theory

Modern VLSI Design 3e: Chapter 2 Copyright  1998, 2002 Prentice Hall PTR Topics n Derivation of transistor characteristics.

1 The Physical Structure (NMOS) Field Oxide SiO2 Gate oxide Field Oxide n+ Al SiO2 Polysilicon Gate channel L P Substrate D S L W (D) (S) Metal n+ (G)

EE213 VLSI Design S Daniels Channel Current = Rate of Flow of Charge I ds = Q/τ sd Derive transit time τ sd τ sd = channel length (L) / carrier velocity.

NOTICES Project proposal due now Format is on schedule page

© Digital Integrated Circuits 2nd Devices Digital Integrated Circuits A Design Perspective The Devices Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic.

Jan M. Rabaey The Devices Digital Integrated Circuits© Prentice Hall 1995 Introduction.

Chapter 5: Field Effect Transistor

Short Channel Effects in MOSFET

1 The Physical Structure (NMOS) Field Oxide SiO2 Gate oxide Field Oxide n+ Al SiO2 Polysilicon Gate channel L P Substrate D S L W (D) (S) Metal n+ (G)

Digital Integrated Circuits© Prentice Hall 1995 Devices Jan M. Rabaey The Devices.

UNIT I MOS TRANSISTOR THEORY AND PROCESS TECHNOLOGY

HO #3: ELEN Review MOS TransistorsPage 1S. Saha Long Channel MOS Transistors The theory developed for MOS capacitor (HO #2) can be directly extended.

CMOS VLSI Design CMOS Transistor Theory

Introduction to CMOS VLSI Design Lecture 4: CMOS Transistor Theory David Harris Harvey Mudd College Spring 2007.

MOSFET Current Voltage Characteristics Consider the cross-sectional view of an n-channel MOSFET operating in linear mode (picture below) We assume the.

Metal-oxide-semiconductor field-effect transistors (MOSFETs) allow high density and low power dissipation. To reduce system cost and increase portability,

Introduction to CMOS VLSI Design CMOS Transistor Theory

Damu, 2008EGE535 Fall 08, Lecture 21 EGE535 Low Power VLSI Design Lecture #2 MOSFET Basics.

CMOS VLSI Design 4th Ed. EEL 6167: VLSI Design Wujie Wen, Assistant Professor Department of ECE Lecture 3A: CMOs Transistor Theory Slides adapted from.

Introduction to MOS Transistors

EE314 IBM/Motorola Power PC620 IBM Power PC 601 Motorola MC68020 Field Effect Transistors.

The Devices: MOS Transistor

UNIT II : BASIC ELECTRICAL PROPERTIES

MOS Capacitance Unit IV : GATE LEVEL DESIGN VLSI DESIGN 17/02/2009

MOS Field-Effect Transistors (MOSFETs)

Floating-Gate Devices / Circuits

DMT 241 – Introduction to IC Layout

MOS TRANSISTOR (Remind the basics, emphasize the velocity saturation effects and parasitics) Structure of a NMOS transistor.

Prof. Haung, Jung-Tang NTUTL

Revision CHAPTER 6.

VLSI design Short channel Effects in Deep Submicron CMOS

Lecture 20 OUTLINE The MOSFET (cont’d) Qualitative theory

Introduction to Metal-Oxide-Semiconductor Field Effect Transistors (MOSFETs) Chapter 7, Anderson and Anderson.

3: CMOS Transistor Theory

積體電路元件與製程半導體物理半導體元件 PN junction CMOS 製程 MOS 元件.

6.3.3 Short Channel Effects When the channel length is small (less than 1m), high field effect must be considered. For Si, a better approximation of field-dependent.

CMOS Inverter First Glance

EE141 Chapter 3 VLSI Design The Devices March 28, 2003.

VLSI System Design Lect. 2.1 CMOS Transistor Theory

The Threshold Voltage The voltage applied between the gate and the source which causes the beginning of the channel surface strong inversion. Threshold.

منبع: & کتابMICROELECTRONIC CIRCUITS 5/e Sedra/Smith

VLSI Design CMOS Transistor Theory

Chapter 1 and 2 review CMOS Devices and models Fabrication process

Short channel effects Zewei Ding.

The Physical Structure (NMOS)

Lecture 3: CMOS Transistor Theory

Lecture 20 OUTLINE The MOSFET (cont’d) Qualitative theory

CP-406 VLSI System Design CMOS Transistor Theory

Lecture #15 OUTLINE Diode analysis and applications continued

Lecture 3: CMOS Transistor Theory

Lecture 3: CMOS Transistor Theory

Copyright © 2004 The McGraw-Hill Companies, Inc. All rights reserved.

MOSCAP Non-idealities

Presentation transcript:

1 Models for Hand Analysis NMOS Transistor PMOS Transistor V DSN  V GSN -V TN V DSN  V GSN -V TN V DSP  V GSP -V TP V DSP  V GSP -V TP K N =(W/L)K’ N K P =(W/L)K’ P

2 pMOS Current model VDSP>VGSP -VTP VDSP <VGSP-VTP

3 Channel Resistance R=

4 Variation of resistance with Vgs

5 LENGTHL SL/S WIDTHW SW/S THIN OXIDEt ox St ox /S DIFFUSION DOPINGNDND 1/SN D. S SUBSTRATE DOPINGNA 1/SN A. S SUPPLY VOLTAGEV DD 1/S V DD /S Linear Scaling

Scalling Effects 6

7 Velocity Saturation and mobility Degradation

8 TOH’s Model for Short Channel for

9 Secondary Effects n Subthreshold current: is the small current that flows from drain at Vgs < Vt n Punch through: If a large voltage is applied to Vds, then the depletion region of the drain can extend to the source, a punch through occurs and under these condition a large current can flow from the drain to source. n Hot carrier: As a results of scaling, device dimensions are reduced while, doping concentrations are increased, while voltages are not reduced to the same proportion, as a consequence there is an increase in electric field in the channel region while, the thickness of the gate insulating layer is thinner. Due to the acceleration of electrons by the Vds, electrons and holes gaining high speed can penetrate the gate insulator and change its characteristics. n Channel hot electrons: If the Vds is increased, then the lateral electric field is increased and the electric field accelerates the electrons near the drain with high kinetic energy they are injected into the oxide near the drain.

10 Semiconductor Resistors Resistance R=  ( l /A) = (  /t). ( l /w ) = Rsh. ( l /w ) Rsh = sheet resistance Ω /  For 0.5u process: N+ diffusion : 70 Ω/  M1: 0.06 Ω/  P+ diffusion : 140 Ω/  M2: 0.06 Ω/  Polysilicon : 12 Ω/  M3: 0.03 Ω/  Polycide:2-3 Ω/  P-well: 2.5K Ω/  N-well: 1K Ω/  w current l t (A)

11 Semiconductor Resistors Al n+ Diffusion n+ Field oxide polysilicon Polysilicon Resistor Diffusion Resistor SiO2

12 Variations in Width and Length W eff W drawn WDWD W D 1. Width Oxide encroachment W eff = W drawn - 2W D 2. Length Lateral diffusion L D = 0.7Xj L eff = L drawn - 2L D L drawn L D L eff L D polysilicon

13 Semiconductor Capacitors 1. Poly Capacitor: a. Poly to substrate b. Poly1 to Poly2 2. Diffusion Capacitor n+ (N D ) depletion region substrate (N A ) bottomwall capacitance sidewall capacitances

14 Transistor Resistance : Two Components: Drain/ Sources Resistance: R D(S) = Rsh x no. of squares+ contact resistance. Channel Resistance : Depends on the region of operation: L W (D) (S) n+ (G) R S Rch R D Linear Saturation

15 Dynamic Behavior of MOS Transistor Prentice Hall/Rabaey

16 The Gate Capacitance Prentice Hall/Rabaey

17 Average Gate Capacitance Most important regions in digital design: saturation and cut-off Different distributions of gate capacitance for varying operating conditions Prentice Hall/Rabaey

18 Diffusion Capacitance Prentice Hall/Rabaey

19 Diffusion Capacitance

20 SPICE TRANSISTOR MODEL

21 SPICE MODELS

22 MAIN MOS SPICE PARAMETERS Prentice Hall/Rabaey

23 SPICE Parameters for Parasitics Prentice Hall/Rabaey

24 SPICE Transistors Parameters Prentice Hall/Rabaey

25 Example