Evaluation of OPA569 Bridge-Tied-Load Errol Leon and Thomas Kuehl Precision Linear Analog Applications February 3, 2016 1.

Slides:



Advertisements
Similar presentations
Digital to Analog Converter By Rushabh Mehta Manthan Sheth.
Advertisements

Differential Amplifiers
Analog Electronics Workshop (AEW) Apr 3, Contents Intro to Tools Input Offset Input and Output Limits Bandwidth Slew Rate Noise EMIRR Filtering.
Galen SasakiEE 260 University of Hawaii1 Building D Flip Flops Combinational circuit components D Clocked Latch: similar to a flip flop but simpler D flip.
NONIDEAL OP AMP CIRCUITS. Objective of Lecture Describe the impact of real operational amplifiers on the models used in simulation and on the design approaches.
Interface & Instrumentation. ADC Sensor Interfacing Gas Sensor Temperature Sensor Humidity Sensor Sonar Sensor.
Practical Differential Amplifier Design We’ve discussed Large signal behaviour Small signal voltage gain Today: Input impedance Output impedance Coupling.
More Non-Ideal Properties Bias Current Offset Voltage Saturation Applications of saturation.
Lecture 9: Operational Amplifiers
Basic Electric Circuits Introduction To Operational Amplifiers Lesson 8.
Astable multivibrators I
Introduction to Op Amps
1 Digital to Analog Converter Nov. 1, 2005 Fabian Goericke, Keunhan Park, Geoffrey Williams.
Control & Monitoring of DC-DC Buck Converters Satish Dhawan Yale University Power Distribution Working Group Meeting- Tuesday 24 February 2009 ATLAS Upgrade.
DC-DC Fundamentals 1.2 Linear Regulator. What is a Linear Regulator? The linear regulator is a DC-DC converter to provide a constant voltage output without.
DATA ACQUISTION AND SIGNAL PROCESSING Dr. Tayab Din Memon Lecture Introduction to Opamps & Multisim.
Digital to Analog Converters
Lab #5 Overview Activity #1 - Simulation of an Op-Amp inverting amplifier Activity #2 - Build and Test the Op-Amp inverting amplifier Activity #3 - Determining.
OPA549 and Negative Whisker on Enable
Composite Amplifier Stability Analysis First Scheme & Second Scheme Tim Green, MGTS Precision Linear Analog Applications August 7,
A Linear Regulator with Fast Digital Control for Biasing of Integrated DC-DC Converters A-VLSI class presentation Adopted from isscc Presented by: Siamak.
OPA348 High Pass Filter Tim Green, MGTS Precision Linear Analog Applications July 9,
LDO or Switcher? …That is the Question Choosing between an LDO or DC/DC Converter Frank De Stasi Texas Instruments.
Linear Regulator Fundamentals
Questions on IFPAC_SCHEMATIC. Signal Chain Preamplifier Compensation Capacitor should go to –Vs, not GND Where is resistor For compensation Network? Does.
Trey Morris Dwalyn Morgan. Requirements 3 stage design gain load impedance input impedance max peak input voltage Maintain harmonic distortions below.
Non - Inverting Amplifier
Experiment 10: Inverting Amplifier With Modifications that Require the Use of the Velleman Oscilloscope.
Power Supply Design. Power Supplies For most electronic devices it is necessary to provide a stable source of DC power. Batteries often serve this function.
ECE 2799 Electrical and Computer Engineering Design “Op-Amp Selection” Prof. Bitar.
Linear Regulator Fundamentals
1 COMPARATORS Function: Compares two input voltages and produces an output in either of two states indicating the greater than or less than relationship.
Evaluation of OPA569 Bridge-Tied-Load Errol Leon and Thomas Kuehl Precision Linear Analog Applications January 26,
EE101-Lecture 8 Operational Amplifier Basics of amplifiers EE101 Fall 2012 Lect 8- Kang1 Noninverting amplifier & Inverting amplifier.
Schmitt Trigger Circuits. Op Amps Previously in ET1 we investigated the Operational Amplifier. The Op Amp consisted of V in V out A feedback loop O V.
5-2-3 Analogue to Digital Converters (ADC). Analogue to Digital Conversion The process is now the opposite of that studied in Topic Now we wish.
Networked Embedded Systems Sachin Katti & Pengyu Zhang EE107 Spring 2016 Lecture 13 Interfacing with the Analog World.
5-3-2 The Emitter Follower. Learning Objectives: At the end of this topic you will be able to;
Analog Electronics Workshop Input/Output Limitations Rev 0.2 March 13, 2013.
More Non-Ideal Properties
Quiz: Determining a SAR ADC’s Linear Range when using Operational Amplifiers TIPL 4101 TI Precision Labs – ADCs Created by Art Kay.
Integrated Shunt-LDO Regulator for FE-I4
Lecture 10 Signals and systems Linear systems and superposition
Electronic Devices Ninth Edition Floyd Chapter 13.
Quiz: Determining a SAR ADC’s Linear Range when using Instrumentation Amplifiers TIPL 4102 TI Precision Labs – ADC Hello, and welcome to the TI Precision.
Feedback Xs Xi Xo + - Xf βf
Quiz: Driving a SAR ADC with a Fully Differential Amplifier TIPL 4103 TI Precision Labs – ADCs Created by Art Kay.
Digital-to-Analog Analog-to-Digital
Feedback No feedback : Open loop (used in comparators)
UNIT-5 Design of CMOS Op Amps.
Task 4 – Report (individual work)
Gentec: 12 Bit Driver for TMS320F2837xD Delfino MCU
High Current V-I Circuits
ME 6405 – Intro to Mechatronics Operational Amplifiers
Presented by: Sanjay Pithadia SEM – Industrial Systems, Medical Sector
Digital Control Systems Waseem Gulsher
Avoid Electrical Overstress (EOS) Op Amps during Power Cycling
OCP Fault Triggered During
Inductive Sensor Analysis
XTR111 Vout or Iout Analysis
Comparators with Hysteresis
Avoid Electrical Overstress (EOS) Op Amps during Power Cycling
Schmitt Trigger Circuits
Comparator Circuits AIM:
Op Amps and Voltage Dividers
Inductive Sensor Analysis
Analog Mixed Signal Fairchild Semiconductor
12 bit SAR driver for TIVA MCU TM4C129ENCPDT
Errol Leon, Analog Applications Precision Linear Analog Applications
OPA2227 All NPN Output Stage Analysis
Presentation transcript:

Evaluation of OPA569 Bridge-Tied-Load Errol Leon and Thomas Kuehl Precision Linear Analog Applications February 3,

OPA569 bridge-tied-load analysis outline 2 1)Simulation with R set of 2.5kΩ and R load of 10Ω 2)I-monitor pin limit as feedback 3)TINA-TI model verification with traditional feedback in place of I MONITOR with an R load of 10Ω 4)Test set-up of customer’s circuit with traditional feedback with an R load of 9.9Ω 5)Test set-up of customer’s circuit with traditional feedback with an R load of 10.2Ω 6)Summary of analysis and recommendation

Simulation with R set at 2.5kΩ and R load at 10Ω 3

TINA-TI schematic of customer circuit with R set 2.5kΩ and R load 10Ω 4

TINA-TI simulation of customer circuit with R set 2.5kΩ and R load 10Ω 5 Note that even though the simulation doesn’t show the I-flag condition, the actual circuit does due to the I MONITOR limit

I MONITOR pin limit as feedback 6

Analysis of I-monitor pin limitations of OPA569 7 Even with R set at 2.5kΩ, the limit of the I MONITOR pin still causes the I-flag condition. From page 13 in the “current monitor” section of the data states: “Additionally, the swing on the I MONITOR pin is smaller than the output swing. When the amplifier is sourcing current, the voltage of the Current Monitor pin must be two hundred millivolts less than the output voltage of the amplifier. Conversely, when the amplifier is sinking current, the voltage of the Current Monitor pin must be at least two hundred millivolts greater than the output voltage of the amplifier.” When condition is violated the current is no longer a linear representation of 1:475 I load. To overcome the I MONITOR pin limit, a traditional voltage feedback configuration using a 2.5kΩ resistor was tested.

Simulation using traditional voltage feedback with R set and R f at 2.5kΩ, and R load at 10Ω 8

TINA-TI schematic of customer circuit with R set and R f are 2.5kΩ and R load is 10Ω using traditional voltage feedback 9

TINA-TI simulation of customer circuit with R set and R f are 2.5kΩ and R load 10Ω using traditional voltage feedback 10 Note symmetry of I load

Test setup of customer circuit with PCB 11 REF5020 voltage regulator was used to generate a V ref of 2V. R load is 10Ω, R cl1 and R cl2 are 14kΩ, R set is 2.5kΩ. Feedback resistor is 2.5kΩ. REF5020 Feedback resistor

Observed “current limit flag” pin and I-load in traditional feedback configuration with an R load of 9.9Ω 12 V in V load + V load - Current Limit Flag “Current limit flag” does not trigger below specified limit and no clipping occurs

Observed “current limit flag” pin and I-load in traditional feedback configuration with an R load of 10.2Ω 13 “Current limit flag” does not trigger below specified limit and no clipping occurs V in V load + V load - Current Limit Flag

Summary of analysis and recommendation 14 I MONITOR must be 200mV from supply as specified on page 13 of datasheet. If violated, I MONITOR no longer holds a linear relationship with I load. This can cause the flag to trigger early and may cause the output to latch at a supply rail. The output is clamping when Vin approaches 0V in the customer’s application circuit. This is due to exceeding the OPA569 output swing limit described on page 3 of the datasheet. Modifying the application circuit to use a traditional voltage feedback configuration resolves the issue encountered when the I MONITOR swing limit is exceeded. It is recommended for the intended input voltage range that a traditional voltage feedback configuration be used in place of the I MONITOR configuration. A feedback resistor value of 2.5kΩ was used for the verification.