1 Memory Systems Caching Lecture 24 Digital Design and Computer Architecture Harris & Harris Morgan Kaufmann / Elsevier, 2007.

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Presentation transcript:

1 Memory Systems Caching Lecture 24 Digital Design and Computer Architecture Harris & Harris Morgan Kaufmann / Elsevier, 2007

2 The Memory Interface

3 The Ideal Memory System

4 Memory Hierarchy

5 Memory Performance Hit: is found in that level of memory hierarchy Miss: is not found (must go to the next level of memory hierarchy)

6 Caches A safe place to hide things What data is stored? How is the data found? What data is replaced?

7 What data is stored?

8 How is data found?

9 Direct-Mapped Cache

10 Direct-Mapped Cache Hardware

11 Direct-Mapped Cache Performance # MIPS assembly code addi $t0, $0, 5 loop: beq $t0, $0, done lw $t1, 0x4($0) lw $t2, 0xC($0) lw $t3, 0x8($0) addi $t0, $t0, -1 j loop done:

12 Direct-Mapped Cache Performance # MIPS assembly code addi $t0, $0, 5 loop: beq $t0, $0, done lw $t1, 0x4($0) lw $t2, 0x24($0) addi $t0, $t0, -1 j loop done:

13 N-Way Set Associative Cache

14 N-way Set Associative Performance # MIPS assembly code addi $t0, $0, 5 loop: beq $t0, $0, done lw $t1, 0x4($0) lw $t2, 0x24($0) addi $t0, $t0, -1 j loop done:

15 Fully Associative Cache

16 Spatial Locality?

17 Increasing Cache Line Size

18 Direct-Mapped Cache Performance # MIPS assembly code addi $t0, $0, 5 loop:beq $t0, $0, done lw $t1, 0x4($0) lw $t2, 0xC($0) lw $t3, 0x8($0) addi $t0, $t0, -1 j loop done:

19 What data is replaced?

20 LRU Replacement # MIPS assembly lw $t0, 0x04($0) lw $t1, 0x24($0) lw $t2, 0x54($0)

21 Caching Summary Temporal and spatial locality LRU or pseudo-LRU replacement Cache Parameters:  C = capacity  b = block size  B = # blocks = C/b  S = number of sets  N = # blocks in a set (# of ways)

22 Next Time Virtual Memory