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MIPS Microarchitecture Pipelined Processor

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Presentation on theme: "MIPS Microarchitecture Pipelined Processor"— Presentation transcript:

1 MIPS Microarchitecture Pipelined Processor
Lecture 21 Digital Design and Computer Architecture Harris & Harris Morgan Kaufmann / Elsevier, 2007

2 Review: Single-Cycle Processor

3 Review: Multicycle Processor

4 Pipeline Processor Activity
Stage 2 - Candy Fetch: Fetch two candybars. Pass them to Stage 3 (the “Execute” stage). Stage 3 – Execute: Keep one candybar and pass the other on to Stage 4, the “Writeback” stage. Stage 4 - Candy “Writeback”: Throw the candybar to the right side of the room. Do not hurt anyone.

5 Single-Cycle vs Pipelined Performance

6 Pipelining Abstraction

7 Single-Cycle and Pipeline Datapath

8 Corrected Pipeline Datapath

9 Pipeline Processor with Control


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