High Gain Transimpedance Amplifier with Current Mirror Load By: Mohamed Atef Electrical Engineering Department Assiut University Assiut, Egypt

Outline Nanometer CMOS Optical Receivers High Gain TIA with Current Mirror Load Post Amplifiers and Output Driver Simulation Results Conclusions

Outline Nanometer CMOS Optical Receivers High Gain TIA with Current Mirror Load Post Amplifiers and Output Driver Post Layout Simulation Results Conclusions

4 Nanometer CMOS Optical Receivers  The TIA is the most critical building block at the optical receiver side in an optical communication system.  CMOS silicon integrated circuits appear to be the best technology that can achieve the required level of integration with reasonable speed, cost, and yield.  As CMOS technology is downscaled, the peak transit frequency of the transistors is increased.  However, the supply voltage of nanometer CMOS chips must be decreased to prevent destructive breakdown in the MOSFETs and to save power in digital circuits.  Also, the transistor output resistance decreased with down scaling the transistors, as a result the intrinsic voltage gain of a transistor will be smaller.

5  Therefore, Multistage TIA is needed for high-gain high-speed amplifiers, which increase the overall power consumption and may affect the amplifier stability.  The CS-TIA sensitivity essentially depends on the input-node capacitance, the transconductance of the input transistors, and therefore the current through them, has to be maximized for minimum noise.  The proposed TIA employs a CS amplifier with a current mirror active load to achieve a high gain and bandwidth at low power consumption.  The proposed TIA employs an CS amplifier with a current mirror active load to achieve a higher gain at lower power consumption than with the normal CS-TIA. Nanometer CMOS Optical Receivers

Outline Nanometer CMOS Optical Receivers High Gain TIA with Current Mirror Load Post Amplifiers and Output Driver Simulation Results Conclusions

High Gain TIA with Current Mirror Load Fig.1. Common source TIA with shunt feedback resistor and current mirror load

High Gain TIA with Current Mirror Load The transimpedance gain transfer function of the TIA in Fig.1 is given by the following relation:

High Gain TIA with Current Mirror Load The transimpedance gain transfer function of the TIA in Fig.1 is given by the following relation: For low frequency the transimpedance gain is As the PD capacitance is larger than the other capacitances (); the bandwidth is determined by the input dominant pole:

Outline Nanometer CMOS Optical Receivers High Gain TIA with Current Mirror Load Amplifiers and Output Driver Post Layout Simulation Results Conclusions

Fig.2. Single ended to differential converter, differential post amplifier and output driver Post Amplifiers and Output Driver

High Gain TIA with Current Mirror Load  The differential output stage is preferred over a single-ended one due to its higher rejection to common mode and power supply noise.  The TIA’s output (single-ended) is fed to the input of single ended to differential the converter (M 1 and R 1 ). The second input of the single-ended to differential converter is biased through a low-pass filter (C s and R s ) coming from the TIA output.  The next stage after the first differential post amplifier is a pre-driver stage (M 2 and R 2 ) to increase the gain and make the interface to the 50Ω driver.  The last stage in the optical receiver is a 50 Ω differential output driver (M 3 and R 3 = 50 Ω) to make the interface between integrated optical receiver chip and the measurement setup.

Outline Nanometer CMOS Optical Receivers High Gain TIA with Current Mirror Load Post Amplifiers and Output Driver Simulation Results Conclusions

Simulation Results  The proposed optical receiver has been integrated in a 130nm CMOS technology with one single supply voltage 1.8V.  The optical receiver is optimized for an off-chip large area photodiode with 1.3pF capacitance and a responsivity of 1 A/W.  The ESD protection and input pad have together a 700fF capacitance. The bonding wires are modeled by 0.7nH inductors. The proposed current mirror load TIA consumes 2.1mA.  The simulated frequency response of the TIA obtained is shown in Fig. 3. The TIA has a bandwidth equal to 1.05 GHz. The transimpedance gain is 64.5 dBΩ

Simulation Results The simulated frequency response of the TIA obtained is shown in Fig. 3. The TIA has a bandwidth equal to 1.05 GHz. The transimpedance gain is 64.5 dBΩ. Fig. 3. Transimpedance gain for proposed current mirror load TIA.

Simulation Results The equivalent input noise current density is shown in Fig.4. The average input referred noise current density is 16pA/√Hz and the integrated input referred noise current is 682nA. Fig. 4. Input noise current density for proposed current mirror load TIA.

Simulation Results A sensitivity of dBm is obtained for the presented optical receiver for BER= at a data rate of 1.25 Gbit/s. Figure 5 shows the eye diagram at 1.25 Gbit/s with PRBS= and an input photodiode current of 9.3µA. Fig. 5. Eye diagram at data rate of 1.25Gbit/s with PRBS = 2 15 – 1 and 9.3 µA peak to peak input photodiode current

Simulation Results The transimpedance bandwidth and gain are calculated for 1000 runs, see Fig. 6. The mean (µ) value of the transimpedance gain is calculated to be dBΩ with standard deviation ( ϭ ) of 1.41 dBΩ, and bandwidth mean value is GHz with standard deviation of MHz. Fig. 6. Monte-Carlo simulation for proposed current mirror load TIA (a) Transimpedance gain (b) Bandwidth

Simulation Results Table I: Comparison with recently published Gigabit implemented CMOS technology

Conclusions  A 1.25 Gb/s high gain transimpedance amplifier in 130 nm CMOS is presented.  The presented TIA shows a 682nA integrated input referred noise current and 3.78 mW power consumption.  The introduced current mirror load TIA shows a high performance compared to the conventional TIAs due to the higher gain coming from the current mirror active load.  By using the active load TIA an optical receiver with higher bandwidth and sensitivity can be designed at low power consumption

21 Mohamed Atef Electrical Engineering Department Assiut University