ATCA based LLRF system design review DESY Control servers for ATCA based LLRF system Piotr Pucyk - DESY, Warsaw University of Technology Jaroslaw Szewinski – Warsaw University of Technology

ATCA based LLRF system design review DESY 2 Agenda Requirements LLRF servers classification ATCA computation power for LLRF servers Servers topology in ATCA based LLRF system Possible control systems Development environment Time schedule and summary

ATCA based LLRF system design review DESY 3 Requirements What servers should do and should not do ? Missing contribution from Jaroslaw Szewinski

ATCA based LLRF system design review DESY 4 What control software do we need? Finite state machines for automation Front-end servers for hardware maintenance, configuration and diagnostics Front-end servers for controller and low level applications (execution nodes for state machines) Middle layer servers for high level applications DAQ servers or interfaces to DAQ GUI panels, interfaces to Matlab, C, etc. Diagnostics maintenanc e End-node for FSM, controller server High level apps, FSM DAQ GUI, external apps

ATCA based LLRF system design review DESY 5 Different CPUs in ATCA based LLRF system Embedded processors AMC module processors ATCA blades mainframes Computation power Huge processing power DAQ, storage Post processing GbE + server class processing power - No PCIe until now + serious processing power - uses AMC slot on carrier + PCIe, GbE - Low processing power - FPGA resources + close to the hardware

ATCA based LLRF system design review DESY 6 FPGA Possible topology of LLRF servers AMC CPU IO AMC (FPGA) FPGA embedded CPU ATCA Carrier board CPU ATCA CPU blade CPU Mainframe blades CPU PCIe GbE Front-end middle layer Simple FSM Front-end middle layer Simple FSM Front- end Middle layer FSM Front-end Middle layer FSM Front-end FSM, DAQ

ATCA based LLRF system design review DESY 7 Possible control systems DOOCS EPICS TINE Dedicated software Missing contribution from Jaroslaw Szewinski

ATCA based LLRF system design review DESY 8 What we can reuse, what we have to develop Reuse –Old communication scheme (one software interface – many hardware drivers), memory description map –Tools for debugging and configuration –Some existing server’s source code New development –Diagnostics, maintenance interfaces (inc. IPMI, crate management) –FSM framework for high level apps –New communication channels

ATCA based LLRF system design review DESY 9 Development environment & tools Linux platform Language parsers, server wizards Scripting languages … Missing contribution from Jaroslaw Szewinski

ATCA based LLRF system design review DESY 10 Schedule, manpower Before we start: –Development environment, control system, communication libraries, FSM framework. Development schedule strongly depends on other tasks –Configuration and maintenance servers (when carrier board and at least one AMC is debugged and ready for firmware implementation ?) –Finite state machines and procedures – starting from ? –Controller server, and low level applications interface servers (parallel to controller development and low level applications) Minimum Manpower –1 fulltime programmer for front-ends, 1 fulltime for FSM and high level apps, 1-2 students for help –A lot of support from MCS group !!!

ATCA based LLRF system design review DESY 11 Backup slides

ATCA based LLRF system design review DESY 12 Old System Scheme FPGA LPT VME ??? Memory map description File / parser TCP Server HardwareChannels EngineUser Applications Internal Interface Eth Other Applications TCP/IP

ATCA based LLRF system design review DESY 13 Linux on PowerPC User applications access hardware through the driver Kernel mode driver has access to the FPGA FPGA has defined hardware interface Virtex II PRO Linux on PPC Hardware FPGA II Core Client on remote machine Kernel mode Internal Interface bus driver User mode TCP server TCP/IP

ATCA based LLRF system design review DESY 14 DOOCS patterns

ATCA based LLRF system design review DESY 15 DOOCS patterns (2)