Firmware and Software for the PPM DU S. Anvar, H. Le Provost, Y.Moudden, F. Louis, E.Zonca – CEA Saclay IRFU – Amsterdam/NIKHEF, 2011 March 30

RTOS DDR2 Memory (64 MB) Flash Memory (32 MB) Processor Boot / FPGA bitstream The KM3Net PPM DU Off-Shore Processor Board Processor PPC440 Slow Control Slow Control Task Slow-Control (SC) for the Storey 1Gb/s Ethernet Link To shore station Data Task Data Time Stamped Data Readout Logic Readout System On Chip (RSOC) One FPGA Component SC Protocol Logic Clock Extraction SCOTT Front End ASICs PMTs x 31 small PMTs TDC TOT Data

Development Setup for the PPM DU Software & Firmware COTS Mini Module VIRTEX-5 FX70 Running vxWorks/ICE ETHERNET Copper SCOTT V1 LINUX PC Run Control Configuration Data Acquisition I2C Humidity/Temperature Sensor SPI DATA UP And RUNNING Pulse Generator Small PMT OCTOPUS Board I2C 1.SCOTT Power On Behaviour on the DAQ testbench 2. Acquired DATA Quality 3. 1 Small PMT + OCTOPUS board plug in and setup 4.ETHERNET Fibre connection and Clock/Command integration TO DOTO DO

Firmware/Lower Level Software Development PowerPC PPC440 I2C Bus 0 Memory Controller I2C Module 0 SPI Module 0 ETHERNET + Clock Controller Custom PMT Readout Module SPI Bus 0 FLASH / SDRAM XILINX FPGA DESIGN XILINX TOOLS GENERATE : FPGA bitstream vxWorks BSP Supported Software drivers (Ethernet, SPI, I2C… ) WindRiver RTOSTOOLS GENERATE : vxWorks boot program vxWorks RTOS image SPI 0/1 ? Custom Logic ? ADCs

Firmware/Lower Level Software Development SCOTT/ARS Bridge XILINX FPGA DESIGN ANTARES Acquisition Module TDC Design /ARS Output MPC860/ PPC440 Bridge PPC440 SCOTT PMT Output SPE like EVENTS (6 Bytes) FPGA software driver adapted from ANTARES SCOTT versus TDC to be study Cross check between a SCOTT channel and a TDC channel (partially Designed)

TDC Firmware Development Synthesized, mapped and routed in a XILINX Virtex-5 FXT70. XILINX routing tools show a 20 ps dispersion in the fast clock arrival times to the 31 samplers. Input LVDS analog data I/O SerDes primitive used as a 1GHz sampler (DDR) channels I/O SerDes primitive used as a 1GHz sampler (DDR) 10 bits PLL MHz Clock input Output parallel sampled data Originally designed by A.Zwart (NIKHEF) / small PMTs test bench for ALTERA Designed by Y.Moudden (CEA) for XILINX

A single TDC Channel IOdelay on the output path to insert a propagation delay 1 to 64 times 78 picoseconds. Validation of proposed single channel TDC architecture. Check for metastability : detect 010 or 101 sequences in the parallel data. None observed. LVDS OUT … … LVDS IN time Sampling frequency 1GHz Output frequency 100 MHz t = t0 + n * 10ns + k * 1ns t0 n k TOT signal

PPM DU Clock distribution Standard Gigabit Ethernet connection to the SOC Gigabit Ethernet connection to standard Ethernet switch Reference Tx Clock 62.5 MHz 62.5MHz Rx Recovered clock Virtex 5 On Shore Virtex 6 Off Shore Phase and Latency Measurements Known-fixed latency link custom logic Commands

PPM DU Clock distribution Off Shore RX TX Gigabit Transceiver GTX in non-standard configuration for fixed-known latency Extraction and insertion of Synchronous commands CUSTOM LOGIC Comma Alignment Embedded hardware Ethernet MAC 1000BASE-X Recovered CLOCK 62.5MHz synchronous of propagated onshore transmission TX Clock with known-fixed phase relationship. PPC440 to shore RxClock : StartRun, ResetCounter: Synchronous commands in the RxClock domain transmitted from and to shore with fixed latency. Customized XPS_LL_TEMAC IP and drivers for Virtex5 FX EDK 12.2 Designed and Tested - To Be Integrated on KOALA test bench

PPM DU (Scalable) High Level Software Run Control Target C&C Electronics C&C Data Sender create /destroy Data Router p p/r Data Filter 1 f 1 f r r Data Manager f Monitoring Run GUI

Network EmbeddedEmbedded EmbeddedEmbedded Communication middleware (ICE) Communication Communication middleware (ICE) Electronic Control Core Concept

DAQ Configuration

DAQ Run Control

CONCLUSION A PPM DU Firmware and Software prototype chain is up and running To be completed (tested apart): –A TDC channel versus a SCOTT channel –An ETHERNET clock and command distribution Next step is to connect a small PMT and (optionally) an OCTOPUS board (I2C control)