Special Features

Device Configuration bits Revision Device Configuration bits Revision On-chip Power-on Reset (POR) Revision On-chip Power-on Reset (POR) Revision Brown-out Reset (BOR) logic Revision Brown-out Reset (BOR) logic Revision Watchdog Timer Revision Watchdog Timer Revision Low power mode (Sleep) Revision Low power mode (Sleep) Revision Internal RC device oscillator Internal RC device oscillator

Device Configuration Bits

The device configuration bits allow each user to customize certain aspects of the device to the needs of the application. When the device powers up, the state of these bits determines the modes that the device uses. Device Configuration Bits These bits are mapped in program memory location 2007h.

bit 13 CP: Flash Program Memory Code Protection bit Protection bit 1 = Code protection off 0 = All program memory code-protected bit 11 bit 11 DEBUG: In-Circuit Debugger Mode bit 1 = In-Circuit Debugger disabled, RB6 and RB7 1 = In-Circuit Debugger disabled, RB6 and RB7 are general purpose I/O pins are general purpose I/O pins 0 = In-Circuit Debugger enabled, RB6 and RB7 0 = In-Circuit Debugger enabled, RB6 and RB7 are dedicated to the debugger are dedicated to the debugger

bit 10-9 WRT1:WRT0 Flash Program Memory Write Enable bits Write Enable bits 11 = Write protection off; all program memory may be written to by EECON control 10 = 0000h to 00FFh write-protected; 0100h to 1FFFh may be written to by EECON control 01 = 0000h to 07FFh write-protected; 0800h to 1FFFh may be written to by EECON control 00 = 0000h to 0FFFh write-protected; 1000h to 1FFFh may be written to by EECON control

bit 8 bit 8 CPD: Data EEPROM Memory Code Protection bit 1 = Data EEPROM code protection off 0 = Data EEPROM code-protected bit 7 LVP: Low-Voltage (Single-Supply) In- Circuit Serial Programming Enable bit Circuit Serial Programming Enable bit 1 = RB3/PGM pin has PGM function; low- voltage programming enabled 0 = RB3 is digital I/O, HV on MCLR must be used for programming

bit 6 BODEN: Brown-out Reset Enable bit 1 = BOR enabled 0 = BOR disabled bit 3 PWRTEN: Power-up Timer Enable bit 1 = PWRT disabled 0 = PWRT enabled bit 2 WDTEN: Watchdog Timer 1 = WDT enabled 0 = WDT disabled

bit 1-0 FOSC1:FOSC0: Oscillator Selection bits 11 = RC oscillator 10 = HS (High speed) oscillator 01 = XT oscillator 00 = LP (Low Power) oscillator

; list directive to define processor list p=16f877a ; list directive to define processor ; processor specific variable definitions #include ; processor specific variable definitions __CONFIG _CP_OFF & _WDT_OFF & _BODEN_OFF & _PWRTE_ON & _XT_OSC & _WRT_OFF & _LVP_OFF & _CPD_OFF & _DEBUG_ON MPASM’s CONFIG Directive

Reset The PIC16F87XA differentiates of Reset: Power-on Reset (POR) Power-on Reset (POR) MCLR Reset during normal MCLR Reset during normal MCLR Reset during Sleep MCLR Reset during Sleep WDT Reset (during normal WDT Reset (during normal WDT Wake-up (during Sleep) WDT Wake-up (during Sleep) Brown-out Reset (BOR) Brown-out Reset (BOR)

Power-on Reset (POR) A Power-on Reset pulse is generated on-chip when VDD rise is detected (in the range of 1.2V-1.7V). Power-up Timer (PWRT) The Power-up Timer provides a fixed 72 ms nominal time-out on power-up only from the POR. Oscillator Start-up Timer (OST) The Oscillator Start-up Timer (OST) provides a delay of 1024 oscillator cycles (from OSC1 input) after the PWRT delay is over (if PWRT is enabled).

Brown-out Reset (BOR) If VDD falls below VBOR (parameter D005, about 4V) for longer than TBOR (parameter #35, about 100 μS), the brown- out situation will reset the device. If VDD falls below VBOR for less than TBOR, a Reset may not occur.

SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT

PCON Register _____ PORBOR bit 1 bit 1 POR: Power-on Reset Status bit 1 = No Power-on Reset occurred 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) bit 0 bit 0 BOR: Brown-out Reset Status bit 1 = No Brown-out Reset occurred 0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)

STATUS BITS AND THEIR SIGNIFICANCE PORBORTOPDCONDITION 0X11 Power-on Reset 1011 Brown-out Reset 1101 WDT Reset 1100 WDT Wake-up 11UU MCLR Reset during normal operation 1110 MCLR Reset during Sleep or Interrupt Wake-up from Sleep

Watchdog Timer & Sleep Mode

Watchdog Timer The Watchdog Timer (WDT) is a free running on-chip RC oscillator which does not require any external components. During normal operation, a WDT time-out generates a During normal operation, a WDT time-out generates a device RESET. device RESET. In SLEEP mode, a WDT time-out causes the device to In SLEEP mode, a WDT time-out causes the device to wake-up and continue with normal operation. wake-up and continue with normal operation.

Watchdog Timer Block Diagram Watchdog Timer WDT Enable Bit POSTSCALER 8 PSA PSA PS2:PS0 From TMR0 To TMR0 To WDT Time Out

OPTION_REG Register (Address 81h,181h) PSAPS2PS1PS0 bit 3 PSA: Prescaler Assignment bit 1 = Prescaler is assigned to the WDT 0 = Prescaler is assigned to the Timer0 module bit 2:0 PS2:PS0: TMR0 Prescaler/WDT Postscaler Rate Select bits

T0CST0ES PSAPS2PS1PS0 bit 5 T0CS: TMR0 Clock Source Select bit 1 = Transition on T0CKI pin 1 = Transition on T0CKI pin 0 = Internal instruction cycle clock (CLKOUT) 0 = Internal instruction cycle clock (CLKOUT) bit 4 T0SE: TMR0 Source Edge Select bit 1 = Increment on high-to-low transition on T0CKI 1 = Increment on high-to-low transition on T0CKI pin pin 0 = Increment on low-to-high transition on T0CKI 0 = Increment on low-to-high transition on T0CKI pin pin

RBPUINTEDG T0CST0ESPSAPS2PS1 bit 6 bit 6 INTEDG: Interrupt Edge Select bit 1 = Interrupt on rising edge of INT pin 1 = Interrupt on rising edge of INT pin 0 = Interrupt on falling edge of INT pin 0 = Interrupt on falling edge of INT pin bit 7 RBPU : Weak Pull-up Enable bit 1 = Weak pull-ups are disabled 1 = Weak pull-ups are disabled 0 = Weak pull-ups are enabled by individual 0 = Weak pull-ups are enabled by individual port latch values port latch values PS0

Watchdog Timer WDT Enable Bit POSTSCALER 8 PSA From TMR0 To TMR0 To WDT Time Out PSA RBPUINTEDGT0CST0ESPSAPS2PS1PS0 OptionRegister X X X X

RBPUINTEDGT0CST0ESPSAPS2PS1PS0 OptionRegister X X X X Watchdog Timer WDT Enable Bit POSTSCALER 8 PSA From TMR0 To TMR0 To WDT Time Out PSA

WDT Period The WDT has a nominal time-out period of 18 ms 18 ms WDT Rate Time-out period WDT Rate Time-out period 1:2 36ms 1:2 36ms 1:3 54ms 1:3 54ms : : : : 1: sec 1: sec

Sleep Mode Sleep (Power-down) mode is a mode where the device is placed in it’s lowest current consumption state. Watchdog Timer will be cleared but keeps running Watchdog Timer will be cleared but keeps running PD bit in the STATUS register is cleared TO bit is set TO bit is set Oscillator driver is turned off Oscillator driver is turned off The I/O ports maintain the status they had, The I/O ports maintain the status they had, before the SLEEP instruction was executed before the SLEEP instruction was executed

The device can wake-up from SLEEP through one of the following events: 1. Any device reset. 2. Watchdog Timer Wake-up (if WDT was enabled). 3. Any peripheral module which can set its interrupt flag while in sleep, such as: while in sleep, such as: - External INT pin - Change on port pin - Comparators - A/D - Timer1 - LCD - SSP - Capture

Wake-up Using Interrupts When interrupts are globally disabled (GIE cleared) and any interrupt source has both its interrupt enable bit and interrupt flag set, one of the following events will occur: If the interrupt occurs before the execution of a SLEEP instruction, the SLEEP instruction will complete as an NOP. Therefore, the WDT and WDT postscaler will not be cleared, the TO bit will not be set and PD bit will not be cleared. If the interrupt occurs during or after the execution of a SLEEP instruction, the device will immediately wake-up from sleep. The SLEEP instruction will be completely executed before the wake-up. Therefore, the WDT and WDT postscaler will be cleared, the TO bit will be set and the PD bit will be cleared.