6/19/ VLSI Physical Design Automation Prof. David Pan Office: ACES Placement (3)

2 6/19/2016 Outline Wire length driven placement Main methods –Simulated Annealing –Partition-based methods –Analytical methods Timing and congestion consideration during placement Newer trends

3 6/19/2016 Timing Cost  Delay of the circuit is defined as the longest delay among all possible paths from primary inputs to primary outputs.  Interconnection delay becomes more and more important in deep sub-micron regime. Critical Path

4 6/19/2016 PO1 PO2 PO3 PI1 PI2 PI netlist with delay for each gate Timing Analysis PO1 PO2 PO3 PI1 PI2 PI arrival times

5 6/19/2016 PO1 PO2 PO3 PI1 PI2 PI arrival time/required time 0/4 0/0 0/8 1/5 3/3 1/9 7/9 9/9 7/15 7/13 13/15 15/15 14/18 18/22 22/22 18/22 PO1 PO2 PO3 PI1 PI2 PI slack = required time - arrival time Timing Analysis

6 6/19/2016 Another example with interconnect delay – Same Timing Analysis LATCHLATCH LATCHLATCH

7 6/19/2016 Timing Driven Placement Approaches Path-based –Most accurate information –Very slow Budgeting –Inaccurate information –Hard to budget –Fast Net-based approach –Net-weighting

8 6/19/2016 Net-Weighting Basic approach –For more timing critical nets (i.e., smaller slack), assign higher net weights –Minimize where

6/19/ H. Ren, D. Z. Pan and D.S. Kung ISPD-04 Sensitivity Guided Netweighting for Placement Driven Synthesis

10 6/19/2016 Figure of Merit (FOM) FOM is the total slack difference compared to a certain slack threshold for all timing end points. Interpreted as the amount of work left for the physical synthesis engine or to the designers for manual fix. FOM and WNS (worst negative slack) are the two most important metrics for timing closure in modern physical synthesis However, FOM was not used to guide placement explicitly

11 6/19/2016 Sensitivity Definitions Net length sensitivity to net weight Net delay sensitivity to net length Net slack sensitivity to net weight: FOM sensitivity to net delay FOM sensitivity to net weight:

12 6/19/2016 Closed-Form Sensitivity For net length to weight sensitivity, we have For delay to wire length sensitivity, we have Use switch-level RC and Elmore delay to illustrate the concept Use switch-level RC and Elmore delay to illustrate the concept Good enough during placement Good enough during placement Can be extended to more accurate models Can be extended to more accurate models

13 6/19/2016 FOM to Net Delay Sensitivity Question: suppose the delay of net i is reduced by a small amount  T(i), what is the impact to FOM? Define: K(i) to be the number of timing end points whose slack will change due to  T(i) Then, we have the following Theorem

14 6/19/2016 K(i) Computation C D (-3, 1) (-3, 2) P o1 P o2 A B (-0.8, 0) (-1.2, 1) (-3, 1) (-0.8, 0) (-1.2, 1) (slack, K(i)) pair Topologically sorted order from PO to PI Only propagate K(i) to the most timing critical input pin

15 6/19/2016 Net Weight Generation Put these sensitivities together and generate new net weight

16 6/19/2016 Experiments We compare the placement and physical synthesis results of three different algorithms on 7 industry chips (up to 444k movable objects) from IBM –WL: wire length driven placement with uniform weight –TS: timing driven placement using slack sensitivity –TSF: timing driven placement using both slack and FOM sensitivity

17 6/19/2016 Timing after Placement

18 6/19/2016 Timing after Physical Synthesis

19 6/19/2016 Outline Wire length driven placement Main methods –Simulated Annealing –Partition-based methods –Analytical methods Timing and congestion consideration Newer trends

20 6/19/2016 Congestion Minimization Traditional placement problem is to minimize interconnection length (wirelength) A valid placement has to be routable Congestion is important because it represents routability (lower congestion implies better routability) There is not yet enough research work on the congestion minimization problem

21 6/19/2016 Definition of Congestion Routing demand = 3 Assume routing supply is 1, overflow = = 2 on this edge. Overflow =  overflow  all edges Overflow on each edge = Routing Demand - Routing Supply (if Routing Demand > Routing Supply) 0 (otherwise)

22 6/19/2016 Correlation between Wirelength and Congestion Total Wirelength = Total Routing Demand

23 6/19/2016 Wirelength  Congestion A congestion minimized placement A wirelength minimized placement

24 6/19/2016 Congestion Map of a Wirelength Minimized Placement Congested Spots

25 6/19/2016 Congestion Reduction Postprocessing Reduce congestion globallyby minimizing thetraditional wirelength Post process the wirelengthoptimized placement usingthe congestion objective

6/19/ An Effective Congestion Driven Placement Framework André Rohe University of Bonn, Germany joint work with Ulrich Brenner ISPD 2002 (Best Paper)

27 6/19/2016 A dense Placement good wirelength impossible to route

28 6/19/2016 Possible Solution easy to route bad wirelength/timing

29 6/19/2016 Congestion Driven Placement easy to route + good wirelength almost no extra computation efford !

30 6/19/2016 Overall Algorithm: Bonn Place Partitioning based approach Solves QP in each level, followed by partitioning Partitioning is done by quadrisection: circuits are partitioned with minimum movement (Vygen)

31 6/19/2016 Methods used for congestion driven placement Very fast congestion calculation Inflate circuits in congested regions Spreading inflated cells

32 6/19/2016 Congestion calculation Calculate Steiner Tree for each net Probablitiy estimation for each 2-point connection (similar to Hung & Flynn, Lou et al.)

33 6/19/2016 Quality of congestion calculation congestion estimation

34 6/19/2016 Quality of congestion calculation Bonn Global HDP Global

35 6/19/2016 Inflation of circuits (used previously by Hou et al.) Initial inflation (based on pin density) Given a circuit c in Region R, c is inflated by up to 100% The inflation is based on the congestion in R and the surrounding regions & the pin density in R Deflation is possible if the circuit is no longer critical.

36 6/19/2016 Placement Step 0

37 6/19/2016 Placement Step 1

38 6/19/2016 Placement Step 2

39 6/19/2016 Placement Step 3

40 6/19/2016 Placement Step 4

41 6/19/2016 Placement Step 5

42 6/19/2016 Placement Step 6

43 6/19/2016 Placement Step 7

44 6/19/2016 Spreading inflated cells Repartitioning considers 2x2 windows in placement grid to optimize netlength Use extra repartitioning step to move cells away from overloaded regions

45 6/19/2016 Summary: Algorithm overview 1.Init: Set window_set := {chip area}, set circuit_list(chip area):={all circuits} 2.Main Loop: While (window size big enough) Solve a QP to minimize quadratic netlength For (each window w in window_set) Quadrisection(w) Repartitioning 3.Legalization

46 6/19/2016 Algorithm overview 1.Init: Set window_set := {chip area}, set circuit_list(chip area):={all circuits} For (each c in {all circuits}) Increase b(c) proportionally to |pins(c)|/size(c) # initial inflation b(c) 2.Main Loop: While (window size big enough) Solve a QP to minimize quadratic netlength For (each window w in window_set) Quadrisection(w) Repartitioning 3.Legalization

47 6/19/2016 Algorithm overview 1.Init: Set window_set := {chip area}, set circuit_list(chip area):={all circuits} For (each c in {all circuits}) Increase b(c) proportionally to |pins(c)|/size(c) # initial inflation b(c) 2.Main Loop: While (window size big enough) Solve a QP to minimize quadratic netlength For (each window w in window_set) Quadrisection(w) Compute congestion and update b(c) # update inflation b(c) Quadrisection(w) Repartitioning 3.Legalization

48 6/19/2016 Algorithm overview 1.Init: Set window_set := {chip area}, set circuit_list(chip area):={all circuits} For (each c in {all circuits}) Increase b(c) proportionally to |pins(c)|/size(c) # initial inflation b(c) 2.Main Loop: While (window size big enough) Solve a QP to minimize quadratic netlength For (each window w in window_set) Quadrisection(w) Compute congestion and update b(c) # update inflation b(c) Quadrisection(w) Reduce overloaded windows # extra repartitioning steps Repartitioning 3.Legalization

49 6/19/2016 Computational Results StandardCongestion Driven ChipCPUlenCPUlenBlow IBM 10:23 h7.2 m0:26 h7.4 m10.2 % IBM 20:26 h7.9 m0:27 h9.0 m6.6 % IBM 33:50 h134 m4:39 h142 m20.1 % IBM 47:08 h241 m7:24 h270 m20.2 % IBM 516:10 h375 m16:37 h406 m57.8 % Mean+8.7 %+8.5%

50 6/19/2016 Computational Results II StandardCongestion Driven ChipHDPovCPUlenHDPovCPUlen IBM :15 h9 m75.500:05 h7.5 m IBM :19 h11.5 m75.400:05 h10.1 m IBM :36 h162 m77.304:51 h164 m IBM :18 h324 m75.202:48 h326 m IBM :57 h512 m :48 h527 m Mean-9 %-73 %-5.2 %

51 6/19/2016 Summary In this module, we cover two important concepts during placement to consider besides wire length –Timing driven placement, using net-weighting A new sensitivity based net weighting in ISPD’04 paper –Congestion minimization (using ISPD’02 as an example) congestion estimation Inflate cells in congested region Spread inflated cells