VI. HIGH-EFFICIENCY SWITCHMODE HYBRID AND MMIC POWER AMPLIFIERS: CAD DESIGN EXAMPLES 1. ADS circuit simulator and its applicability to switchmode parallel-circuit Class-E power amplifier design time domain frequency domain 2. ADS CAD design example: high-efficiency low-voltage two-stage 1.75-GHz GaAs HBT power amplifier for handset application 3. ADS CAD design example: high-efficiency high-power 2.14-GHz inverse Class-F GaN HEMT power amplifiers for base station applications
1. ADS circuit simulator and its applicability to parallel-circuit Class-E power amplifier design: time domain Parallel-circuit Class-E load network consists of lossless parallel dc-feed inductor L, shunt capacitor C, series fundamentally tuned L0C0 resonant circuit with high quality factor (chosen as 20) , and load resistor R Load-network parameters are normalized to supply voltage, frequency and output power (equated to unity) for generalized case Transistor is represented by voltage-controlled switch with off-resistance 1 M and small finite on-resistance, value of which can be varied Input source represents voltage source with pulse train at discrete time steps (as opposed to standard pulse source) which can guarantee that there is no time jitter at pulse edges Transient simulator: stop-time 20 sec for normalized frequency 1 Hz to be sufficient to reach steady-state mode Optimization: gradient with maximum iterations not more than necessary to provide sufficiently fast simulation procedure (3-5) Optimization goals: Class-E ideal zero-voltage and zero-voltage-derivative optimum conditions
1. ADS circuit simulator and its applicability to parallel-circuit Class-E power amplifier design: time domain ADS simulation setup
Waveforms of switch voltage Waveforms of load current 1. ADS circuit simulator and its applicability to parallel-circuit Class-E power amplifier design: time domain Waveforms of switch voltage for 1 Hz normalized frequency, stop time of 20 sec is enough to reach steady-state mode Waveforms of load current
1. ADS circuit simulator and its applicability to parallel-circuit Class-E power amplifier design: time domain Waveforms of switch voltage Class-E ideal zero-voltage and zero-voltage-derivative optimum conditions sweeping switch resistance from 0.01*R_load to 0.21*R_load with step of 0.02*R_load increasing R_load Waveforms of switch current Simulation time of 1.2 hours for 1.6-GHz processor
1. ADS circuit simulator and its applicability to parallel-circuit Class-E power amplifier design: time domain output power P and collector efficiency drop by approximately 45% and 39%, respectively, when ratio rsat /R reaches value of 0.15 = 73.4% for rsat/R = 0.1 capacitance C increases by 29% and inductance L is reduced by 29% relatively their ideal optimum (nominal) values to maximize output power and collector efficiency
1. ADS circuit simulator and its applicability to parallel-circuit Class-E power amplifier design: time domain Class-E zero-voltage and zero-voltage-derivative conditions become non-optimum for finite values of saturation resistance rsat Simulation time of 1.2 hours for 1.6-GHz processor collector efficiency can be greater when maintaining the same optimum load network parameters: = 75.7% for rsat /R = 0.1 ( > 2.3%) = 67.2% for rsat /R = 0.15 ( > 6.2%)
1. ADS circuit simulator and its applicability to parallel-circuit Class-E power amplifier design: frequency domain Parallel-circuit Class-E load network consists of lossless parallel dc-feed inductor L, shunt capacitor C, series fundamentally tuned L0C0 resonant circuit with high quality factor (chosen as 20) , and load resistor R Load network parameters are normalized to supply voltage, frequency and output power (equated to unity) for generalized case Transistor is represented by voltage-controlled switch with off-resistance 1 M and small finite on-resistance value of which can be varied Input source represents voltage source with Fourier-series expansion of periodic square wave used in harmonic-balance simulator Harmonic-balance simulator: number of harmonic is chosen to 100 Optimization: gradient with greater maximum iterations to provide sufficiently fast simulation procedure (10) Optimization goals: maximum collector efficiency
1. ADS circuit simulator and its applicability to parallel-circuit Class-E power amplifier design: frequency domain ADS simulation setup
1. ADS circuit simulator and its applicability to parallel-circuit Class-E power amplifier design: frequency domain collector voltage and current waveforms have smoother on-to-off transitions due to finite number of harmonics Simulation time of 5 sec for 1.6-GHz processor collector efficiency using harmonic-balance simulator is close to collector efficiency using transient simulator: = 96.9% for rsat /R = 0.01 ( < 0.1%)
2. ADS CAD design example: high-efficiency low-voltage two-stage 1 2. ADS CAD design example: high-efficiency low-voltage two-stage 1.75-GHz GaAs HBT power amplifier for wireless application Class-E power amplifier design procedure: transistor selection and definition of its model with linear and nonlinear equivalent circuit parameters (measurements or data sheet) analytical calculation of ideal optimum load network parameters for given supply voltage, output power, and device output capacitance (small-signal collector capacitance at operating bias point as starting value or its large-signal value which is usually 15-20% greater) bias circuit selection to optimize quiescent current and minimize/optimize reference current and variations over temperature for maximum power gain, output power, and power-added efficiency design of input and interstage matching circuits to provide minimum input return loss, maximum power gain, and power-added efficiency with stable operation conditions final circuit optimization to maximize power-added efficiency
2. ADS CAD design example: high-efficiency low-voltage two-stage 1 2. ADS CAD design example: high-efficiency low-voltage two-stage 1.75-GHz GaAs HBT power amplifier for wireless application Assumption: output power Pout = 2 W supply voltage Vcc = 5 V collector efficiency = 80% dc power P0 = 2 W / 0.8 = 2.5 W dc current I0 = 2.5 W / 5 V = 500 mA for current density of 15 mA / 90 m2 5400 m2 with some margin Parallel-circuit Class E: peak current Imax = 2.647I0 = 2.15 A saturation voltage Vsat = 0.3 V power loss Psat = I0Vsat = 150 mW Efficiency degradation 1 Psat /P0 = 0.06 or 6% Total output capacitance Cout = Cce + C0 + Cbc = 6.6 pF
2. ADS CAD design example: high-efficiency low-voltage two-stage 1 2. ADS CAD design example: high-efficiency low-voltage two-stage 1.75-GHz GaAs HBT power amplifier for wireless application Second Class-E stage Low source impedance RS = 5 for excessive output capacitance 6.6 – 3.9 = 2.7 pF: inductance 3 nH LT = 3//1 = 0.75 nH Series resonant circuit parameters for QL = 10 Optimum load network parameters:
2. ADS CAD design example: high-efficiency low-voltage two-stage 1 2. ADS CAD design example: high-efficiency low-voltage two-stage 1.75-GHz GaAs HBT power amplifier for wireless application Stability factor Collector and base voltage waveforms Collector and power-added efficiencies Input device and second stage impedances: real part Power gain and output power to compensate for small device input negative resistance, resistor of 0.35 is connected in series to base, compromising stable operation and power gain
2. ADS CAD design example: high-efficiency low-voltage two-stage 1 2. ADS CAD design example: high-efficiency low-voltage two-stage 1.75-GHz GaAs HBT power amplifier for wireless application Second Class-E stage: matching with 50- load Inductance tuning to maximize efficiency due to non-optimum conditions at harmonics Power gain and collector efficiency Output L-type low-pass matching circuit parameters
2. ADS CAD design example: high-efficiency low-voltage two-stage 1 2. ADS CAD design example: high-efficiency low-voltage two-stage 1.75-GHz GaAs HBT power amplifier for wireless application First Class-AB stage Output resistance to provide Pout = 200 mW Output 50-to-5- high-pass L-type matching-circuit parameters: High-pass input matching with series stabilizing resistor Class-AB biasing
2. ADS CAD design example: high-efficiency low-voltage two-stage 1 2. ADS CAD design example: high-efficiency low-voltage two-stage 1.75-GHz GaAs HBT power amplifier for wireless application First Class-AB stage Small-signal S11 and stability factor Power gain and collector efficiency linear power gain of about 15 dB stability factor K > 1 over entire frequency range maximum collector efficiency of about 72% input return loss better than 20 dB at operating frequency collector efficiency of about 65% at 3-dB gain compression point
Two-stage high-efficiency PA 2. ADS CAD design example: high-efficiency low-voltage two-stage 1.75-GHz GaAs HBT power amplifier for wireless application Two-stage high-efficiency PA combination of first stage with 5- load and second stage with 5- source main attention to interstage matching consisting of two high-pass sections: need small tuning (elements inside circle) because impedances at harmonics are different from 50
2. ADS CAD design example: high-efficiency low-voltage two-stage 1 2. ADS CAD design example: high-efficiency low-voltage two-stage 1.75-GHz GaAs HBT power amplifier for wireless application Two-stage high-efficiency PA Small-signal S11 and stability factor Power gain and power-added efficiency linear power gain of more than 29 dB stability factor K > 2.5 over entire frequency range maximum power-added efficiency of about 68% input return loss better than 13 dB at operating frequency power-added efficiency of about 57.5% at 1-dB gain compression point
2. ADS CAD design example: high-efficiency low-voltage two-stage 1 2. ADS CAD design example: high-efficiency low-voltage two-stage 1.75-GHz GaAs HBT power amplifier for wireless application Two-stage high-efficiency PA short transmission lines replace external lumped inductances
Two-stage high-efficiency PA linear power gain of about 29 dB 2. ADS CAD design example: high-efficiency low-voltage two-stage 1.75-GHz GaAs HBT power amplifier for wireless application Two-stage high-efficiency PA linear power gain of about 29 dB maximum power-added efficiency of 67% and power gain of 22.5 dB at output power of 33.6 dBm power-added efficiency of 63% and power gain of 27 dB at output power of 33 dBm
Harmonic impedance conditions: inductances are taken into account 3. High-efficiency high-power 2.14-GHz inverse Class-F GaN HEMT power amplifiers for base station applications Harmonic impedance conditions: ImZnet(0) = 0 ImZnet(20) = ImZnet(30) = 0 Short for 3rd harmonic: Lout, 1 and 2 Package lead and bondwire inductances are taken into account Znet Open for 2nd harmonic: Cout, Lout, and 1 22
3. High-efficiency high-power 2 3. High-efficiency high-power 2.14-GHz inverse Class-F GaN HEMT power amplifiers for base station applications Optimum load-network impedances at fundamental, second, and third harmonics 23
3. High-efficiency high-power 2 3. High-efficiency high-power 2.14-GHz inverse Class-F GaN HEMT power amplifiers for base station applications Load-network equivalence at fundamental Lumped-to-transmission-line single-frequency equivalence: Design equations for low-pass -type matching circuit when RL > R: 24
Design equation to calculate Z1, 1 + 2: 3. High-efficiency high-power 2.14-GHz inverse Class-F GaN HEMT power amplifiers for base station applications Design equation to calculate Z1, 1 + 2: - at fundamental - at third harmonic For x = 0Lout/Z1 < 0.1: If Z1 = 50 and Lout = 0.35 nH 0LoutZ1 = 0.094 at 2.14 GHz tan-1x = sinx x cosx 1 25
3. High-efficiency high-power 2 3. High-efficiency high-power 2.14-GHz inverse Class-F GaN HEMT power amplifiers for base station applications Inverse Class-F transmission-line load network For sufficiently small Cout and large Lout: 2 0 Design equation to calculate Z1, Z2, and 1: 30 < 1 < 60 2 = 0 26
3. High-efficiency high-power 2 3. High-efficiency high-power 2.14-GHz inverse Class-F GaN HEMT power amplifiers for base station applications 5-W Nitronex GaN HEMT NPTB00004 Pout = 37 dBm, power gain = 15 dB, drain efficiency = 73%, PAE = 70% for Vdd = 25 V 27
3. High-efficiency high-power 2 3. High-efficiency high-power 2.14-GHz inverse Class-F GaN HEMT power amplifiers for base station applications Pout = 36 dBm at Vdd = 28 V Power-added efficiency > 70% Drain efficiency = 82% at Vdd = 32.5 V Power variations < 0.5 dB over 2.11-2.17 GHz 28
Power-added efficiency = 79.8% Power-added efficiency = 69.1% 3. High-efficiency high-power 2.14-GHz inverse Class-F GaN HEMT power amplifiers for base station applications Cree GaN HEMT CGH27060F NXP LDMOSFET BLF6G22LS-75 Pout = 47.3 dBm at Vdd = 32 V Pout = 48.0 dBm at Vdd = 28 V Drain efficiency = 82.3% Drain efficiency = 70.2% Power-added efficiency = 79.8% Power-added efficiency = 69.1% Power gain = 14.3 dB Power gain = 18.0 dB 29