Lec 4-2 Five operations of the machine cycle Fetch- fetch the next program instruction from memory. (PC+1); instruction to IR Decode- decode the instruction.

Slides:



Advertisements
Similar presentations
Chapter 2: Data Manipulation
Advertisements

The CPU The Central Presentation Unit What is the CPU?
The Fetch – Execute Cycle
Machine cycle.
Central Processing Unit
The CPU. Parts of the CPU Control Unit Arithmetic & Logic Unit Registers.
The CPU Revision Typical machine code instructions Using op-codes and operands Symbolic addressing. Conditional and unconditional branches.
CHAPTER 4 COMPUTER SYSTEM – Von Neumann Model
Stored Program Concept: The Hardware View
The processor and main memory chapter 4, Exploring the Digital Domain The Development and Basic Organization of Computers.
Basic Computer Organization, CPU L1 Prof. Sin-Min Lee Department of Computer Science.
Elements of the Computer (How a processor works)
Dale & Lewis Chapter 5 Computing components. Let’s design a computer Generic CPU with registers −Program counter (PC) – 5 bits (size of addresses) −Instruction.
The Computer Processor
Lecture 13 - Introduction to the Central Processing Unit (CPU)
CPU Fetch/Execute Cycle
Basic Operational Concepts of a Computer
AKT211 – CAO 01 - Introduction to Computer Organization and Architecture Ghifar Parahyangan Catholic University August 22, 2011 Ghifar Parahyangan Catholic.
Lecture 3. Diff b/w RAM and Registers Registers are used to hold data immediately applicable to the operation at hand Registers are used to hold data.
Computer Architecture and the Fetch-Execute Cycle
Computer Architecture and the Fetch-Execute Cycle
The CPU Central Processing Unit. 2 Reminder - how it fits together processor (CPU) memory I/O devices bus.
CPU Design. Introduction – The CPU must perform three main tasks: Communication with memory – Fetching Instructions – Fetching and storing data Interpretation.
Computer Architecture Lecture 09 Fasih ur Rehman.
Chapter 8: The Very Simple Computer
2 nd Year - 1 st Semester Asst. Lect. Mohammed Salim Computer Architecture I 1.
Model Computer CPU Arithmetic Logic Unit Control Unit Memory Unit
Fetch-execute cycle.
Computer Systems - Registers. Starter… Discuss in pairs the definition of the following Control Unit Arithmetic and Logic Unit Registers Internal clock.
Computer Structure & Architecture 7b - CPU & Buses.
Computer Architecture 2 nd year (computer and Information Sc.)
Computer Architecture Lecture 03 Fasih ur Rehman.
Dale Roberts Department of Computer and Information Science, School of Science, IUPUI CSCI N305 Information Representation: Machine Instructions.
COMPILERS CLASS 22/7,23/7. Introduction Compiler: A Compiler is a program that can read a program in one language (Source) and translate it into an equivalent.
Computer Systems Organization
System Unit Working of CPU. The CPU CPU The CPU CPU stands for central processing unit. it is brain of computer It is most important component of the.
Dale & Lewis Chapter 5 Computing components
Chapter 6: Computer Components Dr Mohamed Menacer Taibah University
Computer Organization and Assembly Languages Yung-Yu Chuang 2005/09/29
Question What technology differentiates the different stages a computer had gone through from generation 1 to present?
Group 1 chapter 3 Alex Francisco Mario Palomino Mohammed Ur-Rehman Maria Lopez.
Structure and Role of a Processor
Processor Organization and Architecture Module III.
Designing a CPU –Reading a programs instruction from memory –Decoding the instruction –Executing the instruction –Transferring Data to/From memory / IO.
Chapter 2 Data Manipulation © 2007 Pearson Addison-Wesley. All rights reserved.
Central Processing Unit Decode Cycle. Central Processing Unit Current Instruction Register (CIR) I1 The fetch cycle has transferred an instruction from.
CPUz 4 n00bz.
Chapter 20 Computer Operations Computer Studies Today Chapter 20.
3.1.4 Hardware a. describe the function and purpose of the control unit, memory unit and ALU (arithmetic logic unit) as individual parts of a computer;
OCR GCSE Computer Science Teaching and Learning Resources
Lecture 13 - Introduction to the Central Processing Unit (CPU)
System Architecture 1 Chapter 2.
The Processor and Machine Language
Functional Units.
Processor Organization and Architecture
Ghifar Parahyangan Catholic University August 22, 2011
The Little Man Computer
Fundamental Concepts Processor fetches one instruction at a time and perform the operation specified. Instructions are fetched from successive memory locations.
THE FETCH-EXECUTE CYCLE.
GCSE OCR 1 The CPU Computer Science J276 Unit 1
THE FETCH-EXECUTE CYCLE.
A Top-Level View Of Computer Function And Interconnection
Information Representation: Machine Instructions
Objectives Describe common CPU components and their function: ALU Arithmetic Logic Unit), CU (Control Unit), Cache Explain the function of the CPU as.
Computer Architecture
Presentation transcript:

Lec 4-2 Five operations of the machine cycle Fetch- fetch the next program instruction from memory. (PC+1); instruction to IR Decode- decode the instruction stored in the IR. Fetch- fetch the operand to the registers Execute- process the command. Store – write the results of the instruction into main memory.

Instruction Cycle Two steps: * Fetch * Execute

Fetch Cycle Program Counter (PC) holds address of next instruction to fetch Processor fetches instruction from memory location pointed to by PC Increment PC –Unless told otherwise Instruction loaded into Instruction Register (IR) Processor interprets instruction and performs required actions

Execute Cycle Processor-memory –data transfer between CPU and main memory Processor I/O –Data transfer between CPU and I/O module Data processing –Some arithmetic or logical operation on data Control –Alteration of sequence of operations –e.g. jump Combination of above

Example 1: Describe the sequence of events carried out during the machine cycle when executing the following instructions. AddressContents 500LDA ADD STO JMP

Instruction #1 LDA 1000 – Load to the accumulator the contents of the memory location 1000.

:::: LDA ADD 1001STO 1002JMP 510 :::: :::: IR MAR MDR PC TMP ACC 500 CPU MM Address bus Data bus RW LDA 1000 Decode LDA

Instruction #2 ADD 1001 – add the contents of location 1001 and the contents of the accumulator and store the result back in the accumulator.

:::: ADD 1001STO 1002JMP 510 :::: :::: IR MAR MDR PC TMP ACC 501 CPU MM Address bus Data bus RW LDA ADD 1001 Decode Add

Instruction #3 STO 1002 – store the contents of the accumulator to the memory location 1002.

:::: ADD 1001STO 1002JMP 510 :::: :::: IR MAR MDR PC TMP ACC 502 CPU MM Address bus Data bus RW LDA STO 1002 Decode

Instruction #4 JMP 510 – Jump to memory location 510

:::: ADD 1001STO 1002JMP 510 :::: :::: IR MAR MDR PC TMP ACC 503 CPU MM Address bus Data bus RW LDA Decode 10 JMP

Example 2: Describe the sequence of events carried out during the machine cycle when executing the following instructions. AddressContents 100JMP MOV R1 R2Move the contents of register R2 to R1. 201STO 800 R1Store the contents of R1 in memory location 800.

AddressContentsComments 100JMP LDA MPY 1001Multiply the contents of the Accumulator with the contents of the memory location 1001 and store the result back in the Accumulator. 202STO Example 3: