Copyright © 2007 by Pearson Education 1 UNIT 6A COMBINATIONAL CIRCUIT DESIGN WITH VHDL by Gregory L. Moss Click hyperlink below to select: Tutorial for Example 6-1 Tutorial for Example 6-2 Tutorial for Example 6-3

2 Example 6-1 problem statement: Create a comparator circuit to compare the magnitudes of two 2-bit numbers ( A1 A0 and B1 B0 ). The circuit will have three output signals: GT, LT, and EQ. GT will be high to indicate that the 2-bit A value is greater than the 2-bit B value. LT will be high if the 2-bit A value is less than the 2-bit B value. EQ will be high if the two 2-bit values are equal. The desired 3-output function is defined in a truth table shown below. A1A0B1B0GTLTEQ

3 Start Quartus II. Open the New Project Wizard in the File menu. Enter the working directory and name for this project. You will need to create a new project folder named comparator for this project in the qdesigns directory. The name for the project will be the same as the ENTITY name two_bit_compare. Check with your instructor for your working directory details. There are no additional files to add. Specify Family & Device. Check the New Project Wizard Summary and Finish. Start a New Design Project

4 Create a Text Design File Open a New File (File menu or the toolbar button). Select “VHDL File” under “Device Design Files.” OK.

5 Enter Text for Design Type one of the design file solutions for Example 6-1 using the Text Editor. Save the two_bit_compare.vhd file in the comparator folder when finished.

6 Check for Errors Click the Analysis and Synthesis button (or choose “Analyze Current File” in the Processing menu). Quartus will check for syntax errors in the design file and will indicate if the analysis was successful or if errors are found. If you have errors, locate the first error in the design file (double-click message or open the menu by pointing the cursor at the message and clicking the right mouse button, choose “Locate” and then “Locate in Design File”). The error will be highlighted in the design file and the message will describe what is wrong. Make the necessary corrections to the design file and check again for errors. Continue when analysis is successful.

7 Compile the Project Click the Start Compilation button (or open the Processing menu and choose “Start Compilation”). The design will be compiled from the top-level of the project as defined by the current project name listed in the banner at the top of the screen. There is only one design file for this project since it is a “flat design.” If the compilation was successful, click OK. If errors are reported, consult your lab instructor.

8 Simulate the Project Create an input file for the simulator by clicking the New file button on the toolbar or choosing “New” in the File menu. Select “Vector Waveform File” under the “Other Files” tab and click OK. Specify an end time of 160 ms for the simulation file. Open the Edit menu and choose “End Time.” Click OK. Specify a grid size of 10 ms for the simulation file. Open the Edit menu again and choose “Grid Size.” Click OK. Open the View menu and choose “Fit in Window.” Select inputs and outputs for the project simulation using the Node Finder.

9 Simulate (continued) Click the List button in the Node Finder window. Select the desired Input Group and output node Names shown below (hold down the CTRL key while clicking the left mouse button on the node name). Add selected nodes to the Vector Waveform File (point to a selected Node handle in the Node Finder window, hold down the left mouse button, and drag the highlighted nodes to the Name field in the Vector Waveform window). Close the Node Finder window.

10 Simulate (continued) Create the desired input waveforms for the project simulation. Select the time from 40ms to 80ms on input group a by holding down the left mouse button and dragging the cursor through that time on the grid. Release the mouse button and the specified time should be highlighted. Click the Arbitrary Value button in the waveform editing toolbar. Enter the binary value 01 in the dialog box and click OK. The group input value for a will be changed in the timing diagram.

11 Simulate (continued) Next select the time from 80ms to 120ms on a. Change the binary group value to 10. Finally select the last time segment for a (120ms to 160ms) and change the binary group value to 11.

12 Simulate (continued) Select the entire waveform for b (click the left mouse button on the node handle, on the name, or on the value). Click the Count Value button in the waveform editing toolbar. The Count Value dialog box should look like the one below. This will produce a repeating count sequence from 00 to 11 in binary. Click OK. The group input value for b will change in the timing diagram.

13 Simulate (continued) Clicking a Group Expand button + in the Name field will display the individual signals for the selected group. The individual signals can be turned off again by clicking the Group Collapse button -. Save the file as 2bit_compare.vwf.

14 Simulate (continued) Simulate the project by clicking the Start Simulation button in the toolbar or opening the Processing menu and choosing “Start Simulation.” Verify correct operation for this project.

15 Notes on Programming and Testing a PLD Remember to follow the specific instructions given by your instructor for your laboratory equipment. If necessary, manually assign desired pin numbers to input and output signals (Assignments menu > Pins) and recompile. Open the Pin-Out File in the Fitter report to check the pin assignments made by the compiler. Attach the PLD trainer to the PC, power the board, and program the target device. Test the design with the chip’s inputs connected to logic switches and the outputs connected to logic display lamps (wired according to the pin assignments shown in the final Pin-Out File except for pin 83). End Ex. 6-1

16 Example 6-2 problem statement: Design and construct a 2421-BCD-to-5421-BCD code converter. The truth table for this design is given below. The inputs are labeled d c b a and the outputs are labeled p q r s. Note that in this situation, we care about only 10 of the 16 possible input combinations. The other 6 input combinations are listed at the bottom of the truth table and are labeled as “invalid.” Each of the invalid input conditions should be given a default output value of Weights  Value  DCBAPQRS Invalid

17 Start Quartus II. Open the New Project Wizard in the File menu. Enter the working directory and name for this project. You will need to create a new project folder named code_conv for this project in the qdesigns directory. The name for the project will be the same as the ENTITY name code. Check with your instructor for your working directory details. There are no additional files to add. Specify Family & Device. Check the New Project Wizard Summary and Finish. Start a New Design Project

18 Create a Text Design File Open a New VHDL design file. Type one of the design file solutions for Example 6-2 using the Text Editor. Save the code.vhd file in the code_conv folder.

19 Check for Errors Check for syntax errors using “Analysis and Synthesis.” The dialog box will indicate if errors are found. If you have errors, “Locate” them and make the necessary corrections to the design file. Continue when analysis is successful.

20 Compile the Project Start Compilation.

21 Simulate the Project Open a New Vector Waveform File (under “Other Files”). Enter 16.0μs for the End Time (Edit menu). Enter 1μs for the Grid Size (Edit menu). Fit in Window (View menu).

22 Simulate (continued) Open Node Finder window (View menu > Utility Windows). List nodes and select (CTRL-click left mouse button) the Input Group named in and the Output Group named out. Drag to the Vector Waveform window. Close Node Finder.

23 Simulate (continued) Reverse the order of the input port bits so that they are arranged with the MSB on top. Select all four input signals by dragging the cursor through a b c d while holding the left mouse button down. Click the Sort button on the waveform editing toolbar. Select Descending order and click OK.

24 Simulate (continued) Group the input signals together. With the four inputs selected, open the menu by right-clicking the mouse while pointing to the highlighted area. Choose Group. Type input as the Group name in the dialog box and select Hexadecimal as the Radix. Click OK.

25 Simulate (continued) Group the output signals together and give them the Group name output. Select the four output signals, right-click mouse, choose Group, and type output for the Group name. Click OK.

26 Simulate (continued) Create a simulation input waveform that will verify all 16 possible input combinations for this project. Select the entire waveform for input (left-click the handle, name, or value). Click the Count Value button in the waveform editing toolbar to count from 0 to F in Hexadecimal. OK.

27 Simulate (continued) Save the code.vwf file. Start Simulation. Verify correct operation.

28 Simulate (continued) Change the radix for both signal groups in the timing diagram. Select the waveforms (drag the cursor through the handle, name, or value fields while holding the left mouse button down). Right-click the mouse while pointing to the highlighted area to open the menu and choose Properties. Change Radix to Binary in the pull-down list.

29 Final Simulation Results

30 Notes on Programming and Testing a PLD Remember to follow the specific instructions given by your instructor for your laboratory equipment. If necessary, manually assign desired pin numbers to input and output signals (Assignments menu > Pins) and recompile. Open the Pin-Out File in the Fitter report to check the pin assignments made by the compiler. Attach the PLD trainer to the PC, power the board, and program the target device. Test the design with the chip’s inputs connected to logic switches and the outputs connected to logic display lamps (wired according to the pin assignments shown in the final Pin-Out File except for pin 83). End Ex. 6-2

31 Example 6-3 problem statement: Design a 4-channel data selector (multiplexer). The logic expression for this circuit is: __ __ __ __ Y = (D0 S1 S0 + D1 S1 S0 + D2 S1 S0 + D3 S1 S0) EN The four data inputs are D0 through D3, the data channel desired is selected with the input controls S1 and S0, and EN is an enable input.

32 Start Quartus II. Open the New Project Wizard in the File menu. Enter the working directory and name for this project. You will need to create a new project folder named multiplexer_vhdl for this project in the qdesigns directory. The name for the project will be the same as the ENTITY name multiplexer. Check with your instructor for your working directory details. There are no additional files to add. Specify Family & Device. Check the New Project Wizard Summary and Finish. Start a New Design Project

33 Create a Text Design File Open a New VHDL design file. Type one of the design file solutions for Example 6-3 using the Text Editor. Save the multiplexer.vhd file in the multiplexer_vhdl folder.

34 Check for Errors Check for syntax errors using “Analysis and Synthesis.” The dialog box will indicate if errors are found. If you have errors, “Locate” them and make the necessary corrections to the design file. Continue when analysis is successful.

35 Compile the Project Start Compilation.

36 Simulate the Project Open a New Vector Waveform File (under “Other Files”). Enter 40.0ms for the End Time (Edit menu). Enter 2.5ms for the Grid Size (Edit menu). Fit in Window (View menu).

37 Simulate (continued) Open Node Finder window (View menu > Utility Windows). List nodes. Select (CTRL-click left mouse button) the signal nodes shown below. Drag to the Vector Waveform window and close Node Finder.

38 Simulate (continued) Arrange the input signals as shown below. Select a waveform (point to the waveform’s handle, drag up or down to a new location while holding the left mouse button down, and release the button). Expand the d input group to also show the individual input signals. Create some test vector inputs for s (select), en (enable), and d(3) through d(0) (data) by editing the waveforms. Save the file.

39 Simulate (continued) Start Simulation. Verify correct operation. The y output should be equal to the selected (controlled by s value) d input when en (enable) is high. Example results are shown below.

40 Notes on Programming and Testing a PLD Remember to follow the specific instructions given by your instructor for your laboratory equipment. If necessary, manually assign desired pin numbers to input and output signals (Assignments menu > Pins) and recompile. Open the Pin-Out File in the Fitter report to check the pin assignments made by the compiler. Attach the PLD trainer to the PC, power the board, and program the target device. Test the design with the chip’s inputs connected to logic switches and the outputs connected to logic display lamps (wired according to the pin assignments shown in the final Pin-Out File except for pin 83). End Ex. 6-3

41 End Unit 6 Quartus II VHDL Tutorials