Linear Regulator Fundamentals 2.5 PMOS Author's Original Notes:

Linear-Regulator Operation Voltage feedback samples the output R1 and R2 may be internal or external Feedback controls pass transistor’s current to the load V IN REF C OUT R LOAD ERROR AMP PASS TRANSISTOR R1 R2 Every linear regulator uses a configuration similar to the one shown in this figure. The primary difference between all of the linear-regulator topologies is the particular pass-transistor configuration utilized. They affect the following key specifications: DROPOUT VOLTAGE: Dropout voltage, defined as the minimum input-to-output difference of voltage required to keep a linear regulator’s output in regulation, is dependent both on load current and temperature. It is important to note that the electrical performance of the regulator (PSRR, load and line regulation) degrade as the input voltage approaches the point of dropout. A linear regulator will not perform well operated in or very near dropout. GROUND PIN CURRENT: Ground Pin current (also sometimes called quiescent or no load current) is the current used by the device which does not flow to the load. It is measured as the current flowing out of the ground pin. The term “quiescent current” normally means the ground pin current when the regulator is not driving the load (or is in standby mode). POWER SUPPLY RIPPLE REJECTION (PSRR): This specifies how much noise on the input gets filtered out by the control loop of the regulator before reaching the output. In general, wider gain bandwidth means better PSRR. A high value of PSRR at a frequency around 1 kHz is useful in some cell phone applications due to the 800 Hz transmit burst. BROADBAND NOISE: Total noise energy over a specific frequency range is used to specify broadband noise. Lower is always better, and low noise is required for things like PLLs and sensitive analog circuitry. Low Iq regulators can have higher noise because their reference is noisier and contributes the main noise component. Some LDOs attain lower noise performance by connecting the internal reference node to a package pin, allowing a bypass capacitor to be added to reduce reference noise. STABILITY REQUIREMENTS: The various pass transistors affect the loop’s AC characteristics and must be compensated differently. The LDO regulators generally have more restrictive requirements to assure stability in comparison to NPN regulators.

P-FET-LDO Linear Regulators Drop-out voltage set by by FET RDS-ON Very low quiescent (ground pin) current Ground-pin current independent of load To see why using a P-FET in an LDO is advantageous, it should be noted that all of the base current required by the power transistor in a PNP LDO flows out of the ground pin and back to the source- power-supply return. Therefore, this base-drive current is drawn from the input supply but does not drive the load, so it generates wasted power that must be dissipated within the LDO regulator: PWR (Base Drive) = VIN X IBASE The amount of base current required to drive the PNP is equal to the load current divided by the beta (gain) of the PNP, and the beta may be as low as 15-20 (at rated load current) in some PNP-LDO regulators. The wasted power generated by this base drive current is very undesirable (especially in battery-powered applications). Using a P-FET solves this problem, since the gate-drive current is very small. The two main disadvantages of the monolithic P-FET LDO are that the P-FET limits the lowest value of input voltage to about 2.5V, and the large amount of gate capacitance requires the IC designer to make specific circuit accommodations to keep the resulting pole at a high enough frequency that it does not cause instability.

Driving PMOS LDO Pass Element Author's Original Notes:

Gate Drive vs. Low Load Current The Gate to Source voltage for a load current requirement of 50mA

Gate Drive vs. High Load Current Changing the load current requirement to 3.A requires that the Gate to Source voltage be increased.

Summary The PMOS LDO has the following Characteristics: Requires that the input voltage be higher than the output voltage based on the load current and the On Resistance of the pass element: VIN > RDS(on) x IOUT Requires that the output voltage be higher than the VGS requirement of the pass element Requires careful selection of the output capacitor value and ESR ratings To achieve similar RDS(on) performance a PMOS transistor will require a larger die area than NMOS transistors The larger die area will affect pricing, and might affect performance The PMOS pass transistor in the LDO uses the Drain as the output pin. This high impedance output forces the need for a specific capacitor value (uF) with a specific Effective Series Resistance (ESR), to maintain stability across the output load current range. Tantalum capacitors are usually recommended as they are most likely type to have the needed capacitance value and ESR value within a wide temperature range. Aluminum capacitors are usually not recommended, but can be used in a limited temperature environment. New devices are available that have been designed to work with Ceramic Low ESR capacitors.

Thank you! Author's Original Notes: