Electrical Engineering Engineering the Future Digital Circuits Fundamentals Hands-on Full-Adder Simulation (afternoon)

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Presentation transcript:

Electrical Engineering Engineering the Future Digital Circuits Fundamentals Hands-on Full-Adder Simulation (afternoon)

Electrical Engineering: Digital Circuits Fundamentals Binary Numbers Binary Functions Engineering the Future

Decimal Numbers

Binary Numbers

Binary Counting Exercise Count up to ? Using 2 bits Count up to ? Using 3 bits Count up to ? Using 4 bits Count up to ? Using 5 bits Count up to ? Using 6 bits

Binary Numbers

Logic Gates

Logic Gates

Binary Addition Networks (Half Adder) With two’s complement numbers, addition is sufficient Half-adder Schematic SUM CARRY

Binary Addition Networks (Cascaded Multi-bit Adder) usually interested in adding more than two bits this motivates the need for the full adder

Binary Addition Networks (Full Adder) S = A ’ B ’ CI+A ’ BCI+AB ’ CI ’ +ABCI = CI xor A xor B CO = B CI + A CI + A B = CI (A + B) + A B

One-bit adder 1-bit binary adder –inputs: A, B, Carry-in –outputs: Sum, Carry-out A B Cin Cout S ABCinSCout

Binary Addition Networks (Full Adder/ Half Adder) Alternative Implementation: 5 Gates CO = A B + CI (A xor B) = A B + B CI + A CI Standard Approach: 6 Gates SUM CARRY OUT CARRY IN

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