1. Half-Adder:  A combinational circuit which adds two one-bit binary numbers is called a half-adder. oThe sum column resembles like an output of the XOR gate. oThe carry column resembles like an output of the AND gate. www.bookspar.com | Website for Students | VTU NOTES | QUESTION PAPERS1

2. Limitations (disadvantages) of half-adder: oIn multi-digit addition we have to add two bits along with the carry of previous digit addition. Such addition requires addition of 3 bits. This is not possible in half-adders. www.bookspar.com | Website for Students | VTU NOTES | QUESTION PAPERS2

3. Full Adder: oIn a full adder, three bits can be added at a time. The third bit is a carry from a less significant column. www.bookspar.com | Website for Students | VTU NOTES | QUESTION PAPERS3

4. Alternate Representation of Full-Adder: www.bookspar.com | Website for Students | VTU NOTES | QUESTION PAPERS4

5. Parallel Binary Adder oWhile we add the LSB, there is no carry to be handled and thus, only a half adder is used for this stage. oFor any other bit addition, there may be a carry from the preceding stage and thus, full adders are used for these stages. www.bookspar.com | Website for Students | VTU NOTES | QUESTION PAPERS5

6. Example: www.bookspar.com | Website for Students | VTU NOTES | QUESTION PAPERS6