Development and Implementation of Real-time Distributed Network with the CAN Protocol Thesis Defense Walt Ford Thursday, November 10, 2005

Overview Time Scales, briefly CAN Overview Platforms Used CAN Resource Manager for QNX CAN Core for GBA-Xport Conclusion

Approaches control with a new paradigm Evaluates and classifies bus activity Higher bus throughput Time Scales, briefly R hZhZ P ab H0H0 t Time Scales So Far

Physical Real-Time Systems ComputerMotor Sensor Sensor… System Nodes System Communication

Why CAN? Real-time Fast enough for control Flexible Existing technology Existing testing methods hZhZ H0H0

Developed in the 80s by Bosch GmbH For automotive applications Standardized by ISO in 1993 CAN History CAN Hi CAN Lo

The CAN Protocol No specified medium Inherent prioritization Guaranteed latency Message based protocol Robust protocol DominantRecessive

QNX RTOS Real-time Operating System Microkernel Message Passing Resource Managers Microkernel File System Serial Driver Process Manager Application CAN Driver Messages

GBA MHz ARM7 Processor Z80 Processor 240x160 pixel Display Convenient User Input

Xport Created by CharmedLabs Interfaces with internal bus FPGA and Flash memory Supports various peripherals FPGA Flash

XRC and Other Devices More peripherals Code libraries OpenCores.org CAN Controller Core MCP2551 CAN transceiver

QNX CAN Resource Manager ARCOM AIM104-CAN card –SJA1000 CAN controller –Adapted to ISA Can4linux –Multiple CAN controllers –Open source

SJA1000 access functions Connect and I/O functions Interrupt handler Resource manager QNX Resource Manager User Connect functions I/O functions Resource Manager Low-level SJA1000 Access Functions Arcom CAN Card Processing threads ISR

QNX Results Can4qnx API –Well documented –Easily ported to other SJA1000 devices Several QNX Development Environments Familiarity with QNX RTOS

GBA-Xport-CAN Core Interface GBA bus CAN Core bus Interface Additional elements Transceiver GBA FPGA Decoder Logic Interface OpenCores.org CAN Core Transceiver CAN bus RXTX 8051 Style Bus Address Data Out Data In Rd Wr GBA’s 16 bit multiplexed data/address bus

GBA Bus Structure Multiplexed to support legacy cartridges Primary module from CharmedLabs –Address –Rd –Wr –CartData –DataWr

8051 Bus Data and address share the bus Address latch Rd Wr

GBA-CAN Core Interface idle addr1 rwst addr2 Is enable high? No Yes Is Rd or Wr low? No Yes

GBA-CAN Core Interface Rd Wr gaterw Addr[7:0] CartData gateaddr DataRd can_rd can_wr can_io AND MUX TRI-BUF INV can_ale Primary Module CAN Core

Additional functionality CAN Transceiver CAN Core controller class in C++ Interrupts HW Reset CAN CorePower CAN bus

Final Configuration

Other Progress Optical encoder for the Xport Test code for all projects Project documentation Base configuration for EGR5332 lab Lab support

Thesis Results “Can4qnx” code libraries in C –Resource Manager –ISR –SJA1000 Low-level Access Functions “CAN” module interface in Verilog “CCanCore” controller class in C++ Both compatible with standard CAN devices Real-time testbed for the Time Scales NSF research

Concluded