2016-6-91 The Stack An Hong 2015 Fall School of Computer Science and Technology Lecture on Introduction to Computing Systems.

Slides:



Advertisements
Similar presentations
Chapter 10 And, Finally... The Stack. Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display Stack: An Abstract.
Advertisements

Chapter 7 Introduction to LC-3 Assembly Language Assembly Language Assembly Process Using the Editor & Simulator for Assembly Language Programming.
Chapter 10 And, Finally.... Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display A Final Collection of ISA-related.
1 System Calls (TRAPS) and Subroutines Patt and Patel Ch. 9.
Interrupts Chapter 8 – pp Chapter 10 – pp Appendix A – pp 537 &
Chapter 5 The LC-3.
1 Lecture 2: Review of Computer Organization Operating System Spring 2007.
CSS 372 Lecture 1 Course Overview: CSS 372 Web page Syllabus Lab Ettiquette Lab Report Format Review of CSS 371: Simple Computer Architecture Traps Interrupts.
Overview I/O – memory mapped programmed / interrupt driven Traps mechanism & RET Subroutines & JSR & JSRR & RET Interrupt mechanism & RTI.
Chapter 9 Overview Traps mechanism & RET Subroutines & JSR & JSRR & RET Interrupt mechanism & RTI.
LC-3 Instruction Set Architecture (Textbook’s Chapter 5)
Chapter 8 I/O. Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display. 8-2 I/O: Connecting to Outside World So far,
S. Barua – CPSC 240 CHAPTER 10 THE STACK Stack - A LIFO (last-in first-out) storage structure. The.
1 Computer System Overview OS-1 Course AA
Chapter 5 The LC-3 LC-3 Computer Architecture Memory Map
Chapter 6 Programming in Machine Language The LC-3 Simulator
Chapter 9 & 10 Subroutines and Interrupts. JSR Instruction: JSR offset (11 bit) xxxxxxxxxxx [PC ]  R7, JMP Offset Jump to Subroutine at offset.
Midterm Tuesday October 23 Covers Chapters 3 through 6 - Buses, Clocks, Timing, Edge Triggering, Level Triggering - Cache Memory Systems - Internal Memory.
Chapters 9 & 10 Midterm next Wednesday (11/19) Trap Routines & RET Subroutines (or Functions) & JSR & JSRR & RET The Stack SSP & USP Interrupts RTI.
CSS 372 Oct 2 nd - Lecture 2 Review of CSS 371: Simple Computer Architecture Chapter 3 – Connecting Computer Components with Buses Typical Bus Structure.
S. Barua – CPSC 240 CHAPTER 8 I/O How are I/O devices identified? Memory-mapped vs. special instructions.
Chapter 9 Trap Routines & RET Subroutines (or Functions) & JSR & JSRR & RET.
Chapter 8 Overview Programmed I/O Introduction to Interrupt Driven I/O Project 3.
Chapter 8 I/O Programming Chapter 9 Trap Service Routines Programmed I/O Interrupts Interrupt Driven I/O Trap Service Routines.
Chapter 9 Trap Routines TRAP number (go to service routine) & RET (return from service routine) Subroutines (or Functions) JSR offset or JSRR rn (go to.
Chapters 4 & 5: LC-3 Computer Architecture Machine Instructions Assembly language Programming in Machine and Assembly Language.
Midterm Wednesday 11/19 Overview: 25% First Midterm material - Number/character representation and conversion, number arithmetic - DeMorgan’s Law, Combinational.
Chapter 10 The Stack l Stack data structure l Interrupt I/O l Arithmetic using a stack.
1 CSC 2405: Computer Systems II Spring 2012 Dr. Tom Way.
Introduction to Computing Systems from bits & gates to C & beyond Chapter 8 Input/Output Basic organization Keyboard input Monitor output Interrupts DMA.
Chapter 10 And, Finally... The Stack. Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display Stacks A LIFO.
Chapter 10 The Stack Stack: An Abstract Data Type An important abstraction that you will encounter in many applications. We will describe two uses:
Chapter 10 And, Finally... The Stack Stack: An Abstract Data Type An important abstraction that you will encounter in many applications. We will.
Introduction to Computer Engineering ECE/CS 252, Fall 2010 Prof. Mikko Lipasti Department of Electrical and Computer Engineering University of Wisconsin.
Chapter 8 I/O. Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display. 8-2 I/O: Connecting to Outside World So far,
Chapter 5 The LC Instruction Set Architecture ISA = All of the programmer-visible components and operations of the computer memory organization.
Introduction to Computing Systems from bits & gates to C & beyond Chapter 10 The Stack Stack data structure Activation records and function invocation.
Chapter 5 The LC Instruction Set Architecture ISA = All of the programmer-visible components and operations of the computer memory organization.
Lecture 1: Review of Computer Organization
Interrupt driven I/O Computer Organization and Assembly Language: Module 12.
Introduction to Computing Systems from bits & gates to C & beyond Chapter 10 The Stack Stack data structure Interrupt I/O (again!) Arithmetic using a stack.
Introduction to Computing Systems and Programming The LC-2.
Chapter 8 Input/Output An Hong 2015 Fall School of Computer Science and Technology Lecture on Introduction to.
Chapter 10 And, Finally... The Stack
Chapter 8 I/O.
Chapter 9 TRAP Routines and Subroutines
Computer Science 210 Computer Organization
The Stack.
Chapter 10 And, Finally... The Stack
Chapter 8 I/O.
Chapter 8 Input/Output I/O basics Keyboard input Monitor output
Chapter 9 TRAP Routines and Subroutines
Chapter 10 The Stack.
Arithmetic using a stack
Chapter 8 I/O.
Chapter 9 TRAP Routines and Subroutines
Computer Science 210 Computer Organization
Introduction to Computer Engineering
Chapter 9 TRAP Routines and Subroutines
Chapter 8 I/O.
Chapter 10 And, Finally... The Stack
Chapter 9 TRAP Routines and Subroutines
TRAP Routines Privileged Instructions Subroutines
Chapter 9 TRAP Routines and Subroutines
Chapter 8 I/O.
Chapter 9 TRAP Routines and Subroutines
Chapter 9 TRAP Routines and Subroutines
Chapter 9 TRAP Routines and Subroutines
Presentation transcript:

The Stack An Hong 2015 Fall School of Computer Science and Technology Lecture on Introduction to Computing Systems

Review: Using Memory Memory Just a big “array” “Indexed” by address Accessed with loads and stores LD/LDR/LDI Read a word out of memory Use different addressing mode ST/STR/STI Place a word in memory Use different addressing mode

Review: Using Memory Problem What if the memory you want to access is far away? LD/ST won’t work (PC-relative) LDR/STR won’t work alone (need to get address in register) Solution:LDI/STI Place address of far away value nearby Load address, then load/store from that

Recursion Need Per-subroutine-invocation data space (activation record) Approach Allocate new activation record on a stack whenever a subroutine is called Subroutine uses its own activation record to hold invocationspecific data (e.g., local variables, saved registers) Note Given that Breakout is recursive, we will need activation records

Recursion What’s the problem with... recursion? Each subroutine invocation gets its own activation record... but how? First call to Foo (SaveR7 contains address of Next) Second call to Foo (SaveR7 contains address of After) First return from Foo (returns to After) Second return from Foo (returns to After again!!!)

Stack Data Structure A LIFO (last-in first-out) storage structure The first thing you put in is the last thing you take out The last thing you put in is the first thing you take out Two main operations PUSH: add an item to the stack POP: remove an item from the stack Error conditions: Underflow (try to pop from empty stack) Overflow (try to push onto full stack) A register (eg. R6) holds address of top of stack (TOS)

A Physical Stack Coin holder Last quarter in is the first quarter out (LIFO)

A Software Stack Data items don't move in memory, just our idea about where TOP of the stack is By convention, R6 holds the Top of Stack (TOS) Pointer (SP) x3FFF x4000 x4001 x4002 x4003 x4004

Basic Push and Pop Code Note: Stacks can grow in either direction (toward higher address or toward lower addresses) x3FFF x4000 x4001 x4002 x4003 x4004 PUSH ADD R6, R6, #1; increment stack ptr STR R0, R6, #0; store data(R0) to TOS POP LDR R0, R6, #0; load data(R0) from TOS ADD R6, R6, #-1; decrement stack ptr

Pop with Underflow Detection If we try to pop too many items off the stack, an underflow condition occurs. Check for underflow by checking TOS before removing data. Return status code in R5 (0 for success, 1 for underflow) POP LD R1, EMPTY ADD R2, R6, R1 ; Compare stack pointer BRz UNDER ; with x3FFF LDR R0, R6, #0 ; The actual ‘pop’ ADD R6, R6, #-1 ; Adjust stack pointer AND R5, R5, #0 ; Success: return R5 = 0 RET UNDER AND R5, R5, #0 ; Underflow: return R5 = 1 ADD R5, R5, #1 RET EMPTY.FILL xC001; EMPTY = -x3FFF

Push with Overflow Detection If we try to push too many items onto the stack, an overflow condition occurs. Check for underflow by checking TOS before adding data. Return status code in R5 (0 for success, 1 for overflow) PUSH LD R1, FULL ADD R2, R6, R1 ; Compare stack pointer BRz OVER ; with x4004 ADD R6, R6, #1; Adjust stack pointer STR R0, R6, #0 ; The actual ‘push’ AND R5, R5, #0 ; Success: return R5 = 0 RET OVER AND R5, R5, #0 ADD R5, R5, #1; Overflow: return R5 = 1 RET FULL.FILL xBFFC ; FULL = -x4004

PUSH & POP in LC POPST R2,Sv2; save, needed by POP ST R1,Sv1; save, needed by POP LD R1, EMPTY ; EMPTY contains –x3FFF ADD R2, R6, R1 ; Compare stack pointer with x3FFF BRz Fail_exit; Branch if stack empty LDR R0, R6, #0 ; The actual ‘pop’ ADD R6, R6, #-1 ; Adjust stack pointer RET EMPTY.FILL xC001; EMPTY = -x3FFF PUSHST R2,Sv2; save, needed by PUSH ST R1,Sv1; save, needed by PUSH LD R1, FULL ADD R2, R6, R1 ; Compare stack pointer BRz Fail_exit ; with x4004 ADD R6, R6, #1; Adjust stack pointer STR R0, R6, #0 ; The actual ‘push’ RET FULL.FILL xBFFC ; FULL = -x4004

PUSH & POP in LC Sv1.FILL x0000 Sv2.FILL x0000 Success_exit LD R1, Sv1 ;Restore reg values LD R2, Sv2 ; AND R5, R5, #0 ; Success: return R5 = 0 RET ; Fail_exit LD R1, Sv1;Restore reg values LD R2, Sv2 AND R5, R5, #0 ADD R5, R5, #1; Overflow: return R5 = 1 RET

Arithmetic Using a Stack Instead of registers, some ISA's use a stack for source and destination operations: a zero-address machine. Example: ADD instruction pops two numbers from the stack, adds them, and pushes the result to the stack. ADD vs. ADD R0,R1,R2 Evaluating (A+B)·(C+D) using a stack: push A push B ADD push C push D ADD MULTIPLY pop result x3FFA x3FFB x3FFC x3FFD x3FFE x3FFF x3FFA SP

(25+17) x (3+2) 25 x3FFB x3FFC x3FFD x3FFE x3FFF x3FFA SP x3FFC x3FFB x3FFC x3FFD x3FFE x3FFF x3FFA SP x3FFB x3FFC x3FFD x3FFE x3FFF x3FFA SP 42 3 x3FFC x3FFB x3FFC x3FFD x3FFE x3FFF x3FFA SP x3FFD x3FFB x3FFC x3FFD x3FFE x3FFF x3FFA SP x3FFC x3FFB x3FFC x3FFD x3FFE x3FFF x3FFA SP x3FFB x3FFC x3FFD x3FFE x3FFF x3FFA SP x3FFA x3FFB x3FFC x3FFD x3FFE x3FFF x3FFA SP

Data Type Conversion I/O Keyboard input routines read ASCII characters (not binary values) Console output routines write ASCII (‘s’ not “x73”) Consider this program: TRAP x23 ; input from keyboard ADD R1, R0, #0 ; move to R1 TRAP x23 ; input from keyboard ADD R0, R1, R0 ; add two inputs TRAP x21 ; display result TRAP x25 ; HALT User inputs ‘2’ and ‘3’ -- what happens? Result displayed: ‘e’ Why? ASCII '2' (x32) + ASCII '3' (x33) = ASCII 'e' (x65)

ASCII to Binary Single digit numbers are trivial (subtract x30) E.g., ‘7’ is ASCII x37, x37 - x30 = x7 Input Assume we've read three ASCII digits (e.g., "259") into a memory buffer How do we convert this to a number we can use? Convert first character to digit (subtract x30) and multiply by 100 Convert second character to digit and multiply by 10 Convert third character to digit Add the three digits together

ASCII to Binary Conversion Algorithm

Multiplication How can we multiply a number by 100? Approach 0 -Use the MUL instruction Approach 1 -Add to itself 10 times Approach 2 -Add 10 to itself times (better if number < 10) Approach 3 -Look it up! Only practical if number of multiplicands is small

Code for Lookup Table ; multiply R0 by 100, using lookup table ; LEA R1, Lookup100 ; R1 = table base ADD R1, R1, R0 ; add index (R0) LDR R0, R1, #0 ; load from M[R1]... Lookup100.FILL #0 ; entry 0.FILL #100 ; entry 1.FILL #200 ; entry 2.FILL #300 ; entry 3.FILL #400 ; entry 4.FILL #500 ; entry 5.FILL #600 ; entry 6.FILL #700 ; entry 7.FILL #800 ; entry 8.FILL #900 ; entry 9

Complete ASCII to Binary Conversion Code ASCII "259” to value ASCIIBUF 3 R1

Complete ASCII to Binary Conversion Code (1 of 3) ; Three-digit buffer at ASCIIBUF. ; R1 tells how many digits to convert. ; Put resulting decimal number in R0. ASCIItoBinary AND R0, R0, #0 ;clear result ADD R1, R1, #0 ;test # digits BRz DoneAtoB;done if no digits ; LD R3, NegZero ;R3 = -x30 LEA R2, ASCIIBUF;ptr to the first digit ADD R2, R2, R1;R2 =(R2)+(R1) ADD R2, R2, #-1 ;points to ones digit ; LDR R4, R2, #0 ;load digit ADD R4, R4, R3 ;convert to number ADD R0, R0, R4 ;add ones contribution ;

Complete ASCII to Binary Conversion Code(2 of 3) ADD R1, R1, #-1 ;one less digit BRz DoneAtoB ;done if zero ADD R2, R2, #-1 ;points to tens digit ; LDR R4, R2, #0 ;load ‘tens’ digit ADD R4, R4, R3 ;convert to number LEA R5, Lookup10 ;multiply by 10 ADD R5, R5, R4 LDR R4, R5, #0 ADD R0, R0, R4 ;adds tens contribution to total ; ADD R1, R1, #-1 ;one less digit BRz DoneAtoB ;done if zero ADD R2, R2, #-1 ;points to hundreds digit ; LDR R4, R2, #0 ;load digit ADD R4, R4, R3 ;convert to number LEA R5, Lookup100 ;multiply by 100 ADD R5, R5, R4 LDR R4, R5, #0 ADD R0, R0, R4 ;adds 100's contrib

Complete ASCII to Binary Conversion Code(3 of 3) DoneAtoB RET NegZero.FILL xFFD0 ;-x30 ASCIIBUF.BLKW 4 Lookup10.FILL #0.FILL #10.FILL #20... Lookup100.FILL #0.FILL #100.FILL #200...

Binary to ASCII Conversion Converting a 2's complement binary value to a three-digit decimal number Resulting characters can be output using OUT Instead of multiplying, we need to divide by 100 to get hundreds digit. Why wouldn't we use a lookup table for this problem? Subtract 100 repeatedly from number to divide. First, check whether number is negative. Write sign character (+ or -) to buffer and make positive.

Binary to ASCII Conversion Code (1 of 3) ; R0 is between -999 and ; Put sign character in ASCIIBUF, followed by three ; ASCII digit characters. BinaryToASCII LEA R1, ASCIIBUF ;ptr to result string ADD R0, R0, #0 ;test sign of value BRn NegSign LD R2, ASCIIplus ;store '+' STR R2, R1, #0 BR Begin100 NegSign LD R2, ASCIIneg ;store '-' STR R2, R1, #0 NOT R0, R0 ;convert value to pos ADD R0, R0, #1 Begin100 LD R2, ASCIIoffset LD R3, Neg100 Loop100 ADD R0, R0, R3 BRn End100 ADD R2, R2, #1 ;add one to digit BR Loop100

Binary to ASCII Conversion Code(2 of 3) End100STR R2, R1, #1 ;store ASCII 100's digit LD R3, Pos100 ADD R0, R0, R3 ;restore last subtract ; LD R2, ASCIIoffset LD R3, Neg10 Loop100 ADD R0, R0, R3 BRn End10 ADD R2, R2, #1 ;add one to digit BR Loop10 End10STR R2, R1, #2 ;store ASCII 10's digit ADD R0, R0, #10 ;restore last subtract ; LD R2, ASCIIoffset ADD R2, R2, R0 ;convert one's digit STR R2, R1, #3 ;store one's digit RET ;

Binary to ASCII Conversion Code(3 of 3) ASCIIplus.FILL x002B ;plus sign ASCII code ASCIIneg.FILL x002D ;neg sign ASCII code ASCIIoffset.FILL x0030 ;zero’s ASCII code Neg100.FILL xFF9C ;-100 Pos100.FILL x0064;100 Neg10.FILL xFFF6 ;-10

Interrupt-Driven I/O Timing of I/O controlled by device 1. Report: Tells processor when something interesting happens -Example: when character is entered on keyboard -Example: when monitor is ready for next character -Example: when block has been transferred from disk to memory 2. Processing: Processor interrupts its normal instruction processing and executes a Interrupt Service Routine(ISR) (like a TRAP) -1. Figure out what device is causing the interrupt -2. Execute routine to deal with event -3. Resume execution No need for processor to poll device Can perform other useful work Interrupt is an unscripted subroutine call, triggered by an external event

Interrupt-Driven I/O Program A is executing instruction n Program A is executing instruction n+1 Program A is executing instruction n+2 Program A is executing instruction n+3 Program A is executing instruction n+4 ……

Interrupt-Driven I/O Program A is executing instruction n Program A is executing instruction n+1 Program A is executing instruction n+2 Interrupt!!! Program A is executing instruction n+3 Program A is executing instruction n+4 ……

Interrupt-Driven I/O Program A is executing instruction n Program A is executing instruction n+1 Program A is executing instruction n+2 1.Interrupt signal is detected 1.Program A is put into suspended animation 2.The needs os the I/O device start being carried out 2.The needs os the I/O device being carried out 3.Program A is brought back to life Program A is executing instruction n+3 Program A is executing instruction n+4 ……

When to Use Interrupts When timing of external event is uncertain Example: incoming packet from network TRAP vs. Interrupt, 12.5s vs. 100 char read from KB When device operation takes a long time Example: start a disk transfer, disk interrupts when transfer is finished processor can do something else in the meantime When event is rare but critical Example: building on fire -- save and shut down!

How is Interrupt Signaled? External interrupt signal by Devices: INT Device sets INT=1 when it wants to cause an interrupt Interrupt vector: INTV 8-bit signal for device to identify itself Also used as entry into Interrupt Vector Table, which gives starting address of Interrupt Service Routine (ISR) -Just like Trap Vector Table and Trap Service Routine -TVT: x0000 to x00FF -IVT: x0100 to x01FF

Interrupt Signal to CPU Several things must be true for an I/O device to actually interrupt the processor (ALL the three elements are present) The I/O device must want service(ready bit = 1) The device must have the right to request the service(interrupt enable bit = 1). The device request must be more urgent than what the processor is currently doing

Interrupt Signal to CPU At the device side(I/O device set) Control register has “Interrupt Enable” bit Must be set for interrupt to be generated At the processor(CPU set) Sometimes have “Interrupt Mask” register (LC-3 does not) When set, processor ignores INT signal Why? - Example: may not want to be interrupted while in ISR KBSR I/O device set: ready bit 13 CPU set: interrupt enable bit interrupt signal to processor(INT)

The State of a Program PrPLNZPPSR Cond Codes Priority Level The Processor Status Register PSR[15] 0, privileged (supervisor) mode 1, unprivileged(user)mode The Priority Level of a program being executed PL[10:8] 0( 最低 )~7( 最高 ) Priv Mode

Interrupt Signal to CPU PL1 Device PL2 Device PL7 Device Priority encoder INT B A ? A>B PL of executing program …... What if more than one device wants to interrupt? External logic controls which one gets to drive signals

Testing for Interrupt Signal CPU looks at signal between STORE and FETCH phases If not set, continues with next instruction If set, transfers control to interrupt service routine EA OP EX S S F F D D interrupt signal? Transfer to ISR Transfer to ISR NO YES

How Does Processor Handle It? Examines INT signal just before starting FETCH phase If INT=1, don’t fetch next instruction Instead -Save program state (PC, PSR (privilege and CCs)) on stack -Update PSR (set privilege bit) -Index INTV into IVT to get start address of ISR (put in PC) After service routine RTI instruction restores PSR and PC from stack Need a different return instruction, because  RET gets PC from R7 and doesn’t update PSR -RTI gets PC from R7 and always clears privilege bit in PSR Processor only checks between STORE and FETCH phases -- Why?

Supervisor Mode and the Stack Problem PC and PSR shouldn’t be saved on user stack What if R6 is uninitialized? What if user has set R6 to refer to OS memory? User could see OS data (when trap returns) Solution Create two versions of R6 (stack pointer) in register file  One is user stack pointer (what we’ve been using all along) -The other is supervisor stack pointer Extra register file logic selects the appropriate register based on privilege bit in current PSR Bottom line: OS code always uses its own stack

Example (1)

Example (2)

Example (3)

Example (4)

Example (5)

Example (6)

进一步学习 第 章 32 位 CPU 设计,~50 条指令 RDMA 竞赛 全国并行应用优化大赛 ISC-SCC 国际大学生超算竞赛 SC-SCC 国际大学生超算竞赛

感谢大家对这门课教学工作的配合与支持 !

祝大家期末考试取得好成绩 !

祝大家新年快乐 !