Page 1 EDP CONFERENCE Session 7: Analog and Analog-mixed-signal (A/AMS) Design Flows Current Analog Design Methodologies and Practices Bill Guthrie Numetrics Management Systems, Inc. April 10, 2001

Page 2 Investigating Analog & Mixed-Signal Design Practices What is the definition of an analog or mixed-signal chip? How do AMS chip design projects compare to SoC design projects? What is the AMS content of an SoC design? Are AMS blocks increasing in size? Is AMS design productivity increasing? Data from Numetrics’ Design Productivity Management System database is used to investigate these issues.

Page 3 ASIC Projects DPMS Database Used in This Investigation ASSP Projects No. of Designs 368 Projects As of 27-Mar-01 Design Projects Accumulated in the DPMS Database Data Capture Date

Page 4 Companies Represented in the DPMS Database

Page 5 Characteristics Used to Define & Select AMS Projects in the DPMS Database Projects are included if one of the following criteria is met Analog circuitry contains ≥ 1,000 transistors RF circuitry is used Analog or Mixed-Signal circuitry comprises more than 10% of all transistors BiCMOS or Bipolar process is used Large geometry process is used (≥ 0.6 micron) Only 1 metal layer is used Projects are excluded if one of the following criteria is met Design style is “Gate Array” or “Embedded Array” No Analog, Mixed-Signal, or RF circuitry is used Small geometry process is used (≤ 0.25 micron) High layer count metal system is used (≥ 5 layers)

Page 6 73 Weeks 54 Weeks 51% 49% 61% 39% 1st Tape-out SoC AMS CYCLE TIME TEAM SIZE PEAK FTE AMS SoC Comparison of AMS and SoC Projects Physical Reuse 45% Logical Reuse 22% New Circuitry 33% SIZE, REUSE & COST Physical Reuse 35% Logical Reuse 24% New Circuitry 41% SoC: 4.9M Transistors $2.5M Development Cost AMS: 330K Transistors $780K Development Cost Projects were started in 1998 or later. Sample size is 112 projects.

Page 7 AMS Content in SOC Designs AVERAGE SoC BLOCK COUNT Number of Functional Blocks CPU & Control Interface Mixed Signal Memory DSP & Comm Analog Average Number of Blocks: Logic & Datapath 21.7% Memory 77.8% Analog & Mixed-Signal 0.5% SoC BREAKDOWN BY CIRCUIT TYPE Average Size = 4,900,000 Transistors AMS Content = 24,000 Transistors Based on 72 designs started in 1998 or later

Page 8 New Circuitry Logical Reuse Physical Reuse Effort = 16.3 (Person-weeks) Effort = 13.6 (Person-weeks) 680 2, ,178 1,172 0% 2,400 4,200 4,210 2,396 CAGR = 33% AMS Block Size & Effort AMS Block Size Growth is Due to Reuse 19% 2% 1% 6% 11% 13% 48% 0% 10% 20% 30% 40% 50% 0%1- 20% % % % % 100% Total Reuse per AMS Block Frequency Percentage of Circuitry Reused (Projects started ) Transistor Count Based on sample of 400 AMS blocks

Page 9 AMS Block Design Productivity Trend , ,000 1,500 2,000 2,500 3, Transistors per Person-week CAGR = 33% CAGR = 97% All New AMS Blocks 100% Reused AMS Blocks Productivity does not include adjustments for circuit complexity or effort for chip-level or project-level development tasks.

Page 10 Conclusions AMS Projects are substantially smaller in scope than SoC projects 25% shorter cycle times 65% smaller teams 69% lower development cost SoC designs contain miniscule amounts of AMS circuitry on a percentage transistor basis, but on a block-count basis AMS represents over one-fourth of the design. AMS blocks have grown in size by 33% per year, but all the growth is due to reused circuitry. The productivity of raw AMS transistor design has increased 33% per year for NEW AMS circuitry 97% per year for REUSED AMS circuitry REUSED AMS circuits require only 6% of NEW AMS circuit design effort