High Performance Analog Integrated Circuit Design: The Effect of Device Self- Heating on Design Optimization Ronald L. Carter, Professor Analog Integrated Circuit Design Lab Electrical Engineering Department The University of Texas at Arlington

RLCarter: Analog IC Design with Self Heating2 Analog IC Design with Self-Heating Heat Source/Temperature Effects Thermal Equations/Analogy Thermal Resistance Models Effect of Thermal Resistance on Device Biasing Effect of Thermal Resistance on the Circuit Performance Conclusions/Future Work

RLCarter: Analog IC Design with Self Heating3 Typical IC npn BJT Figure 9.2a, Semiconductor Physics & Devices, 2nd ed., by Neamen, Irwin, Chicago, 1997

RLCarter: Analog IC Design with Self Heating4 EB and CB Heat Sources Figure 9.2a, Semiconductor Physics & Devices, 2nd ed., by Neamen, Irwin, Chicago, 1997 base contact emitter contact collector EB Depletion Region, P E = i E *v BE EB Depletion Region, P C = i C *v BC

RLCarter: Analog IC Design with Self Heating5 Temperature Increase T d -T a =T a {[1 + (n+1)(  e +  c )/T a )] 1/(n+1) 1}  e and  c are pseudo-temperatures via the Kirchoff transformation, assuming k(T) = k(300K)  [T/300] n  e = R Th,EB  |i e v be |  c = R Th,CB  |i c v bc | R Th,EB, R Th,CB are thermal res. at T a. Following S. H. Whemple, and H. Huang, "Thermal Design of Power GaAs FETs", in GaAs FET Principles and Technology, J. V. DiLorenzo and D. D. Khandelwal, eds., pp , Artech House, 1982.

RLCarter: Analog IC Design with Self Heating6 Circuit Simulation of Temperature Effects Typically TNOM (parameter spec. temperature) and TEMP (circuit operation temperature) only variables However, T d =T device is a function of i e, v be, i c and v bc. More flexibility with Vertical Bipolar Inter-Company model (VBIC)

RLCarter: Analog IC Design with Self Heating7 Gummel-Poon Static npn Circuit Model C E B B’B’ ILC ILE IBF IBR I CC - I EC = IS(exp(v BE /NFV t ) - exp(v BC /NRV t )/Q B RC RE RBB Intrinsic Transistor

RLCarter: Analog IC Design with Self Heating8 VBIC Model Overview Self-heating effects included Improved Early effect modeling Quasi-saturation modeling Parasitic substrate transistor modeling Parasitic fixed (oxide) capacitance modeling An avalanche multiplication model included Base current is decoupled from collector current

RLCarter: Analog IC Design with Self Heating9 CAD Tools Support for VBIC Hspice [4] Does not support PNP device Does not scale with “ Area ” and “ M ” terms Spectre [5] Support both NPN and PNP devices scale with “ Area ” and “ M ” term HPADS No temperature nodes ( “ dt ” and “ tl ” ), so unable to simulate thermal coupling effects

RLCarter: Analog IC Design with Self Heating10 Temperature Designations for VBIC 25tnom27tnomParameters measurement temperature 27tref 25 0 Default 27 0 Default Name temp Ambient temperature dtemptriseTemperature rise of the device from ambient Hspice [5] Spectre [4] Parameters Description

RLCarter: Analog IC Design with Self Heating11 Using VBIC in Spectre [5] Name c b e [s] [dt] [tl] ModelName parameter=value... Selft=1 and Rth>0 to enable Self-heating 1 volt at the temperature nodes = 1 degree in temperature “ tl ” node represents the initial local temperature of device which always corresponds to trise+temp “ dt ” node represents the rise above trise+temp caused by thermal dissipation, whose value equals V(dt)-V(tl) Device temperature=V(dt)-V(tl)+trise+temp

RLCarter: Analog IC Design with Self Heating12 Using VBIC in Cadence Need explicit external temperature nodes in the symbol to model inter-device thermal coupling by Connecting thermal network between “ dt ” nodes, or Adding VCVS between “ tl ” and “ tlr ” node Customized VBIC 6-terminal (5-pin) symbol

RLCarter: Analog IC Design with Self Heating13 Model Conversion Most BJTs are defined with SGP model A conversion from SGP to VBIC is needed Only approximate conversion is possible Some parameters are unmapped such as R th and C th Two approaches are provided Manual conversion — done empirically and need Local Ratio Evaluation [2] Program conversion using program sgp_2_vbic [3]

RLCarter: Analog IC Design with Self Heating14 Parameter Mapping using sgp_2_vbic VBICmappingVBICmappingVBICmapping RcxRcMcMjcXtf Rci0CjcpCjsVtf RbxRbmPsVjsItf RbiRb-RbmMsMjsTr Re NeiNfTd  Tf · Ptf/180 Is IbenIseEaEg Nf NenNeEaieEg Nr IbeiIs/BfEaicEg Fc IbciIs/BrEaneEg Cje NciNrEancEg PeVjeIbcnIscXisXti MeMjeNcnNcXiiXti-Xtb CjcCjc · XcjcIkf XinXti-Xtb CjepCjc(1-Xcjc)Ikr KfnKf PcVjcTf AfnAf Early Effect model is different Need Vbe, Vbc to solve the 3 equations below

RLCarter: Analog IC Design with Self Heating15 Analog IC Design with Self-Heating Heat Source/Temperature Effects Thermal Equations/Analogy Thermal Resistance Models Effect of Thermal Resistance on Device Biasing Effect of Thermal Resistance on the Circuit Performance Conclusions/Future Work

RLCarter: Analog IC Design with Self Heating16 Device Geometry and Bound- ary Conditions

RLCarter: Analog IC Design with Self Heating17 Static Heat Flow Equation and Poisson ’ s Equation  T = T-T 0 (K) is the temperature rise above local ambient  = Thermal conductivity (Wcm -1 K -1 ) g= volumetric heat gen. rate (W cm -3 )  = charge dens., and  = permittivity

RLCarter: Analog IC Design with Self Heating18 The Electrical Analogy The Kirchoff transformation factors the  (T) Both equations become the Laplacian  V[Volt] is the analog of  T[K] I[Ampere] is the analog of P [Watts] V = IR is the analog of  T = P R TH

RLCarter: Analog IC Design with Self Heating19 Parameter Name SiSiO 2 AlCu Conductivity  (Wcm -1 K -1 ) Density  (g cm -3 ) Specific Heat C P (Jg -1 K -1 ) Semiconductor Material Properties at 300K

RLCarter: Analog IC Design with Self Heating20 Applying the Analogy to Spreading Resistance The potential field due to a point current source on a wafer surface is V =  I/(2  r) The thermal analogy is T = P/(2  r) For a cylindrical contact of radius r, the spreading resistance, Rsp =  /4r The thermal analogy is Rth = 1/4  r Dieter K. Schroder, “ Semiconductor material and device characterization, 2nd Ed., Wiley-Interscience in 1998, New York Pages

RLCarter: Analog IC Design with Self Heating21 Analog IC Design with Self-Heating Heat Source/Temperature Effects Thermal Equations/Analogy Thermal Resistance Models Effect of Thermal Resistance on Device Biasing Effect of Thermal Resistance on the Circuit Performance Conclusions/Future Work

RLCarter: Analog IC Design with Self Heating22 Thermal Resistance Model for square emitter For a square emitter of side w S. H. Whemple, and H. Huang, op. cit.

RLCarter: Analog IC Design with Self Heating23 Image effect of Heat Sources Below Surface base contact emitter contact collector EB Depletion Region, P E = i E *v BE EB Depletion Region, P C = i C *v BC D

RLCarter: Analog IC Design with Self Heating24 Dielectric Isolated BJT (DIBJT) k Si ~ 100 k Si02 Perimeter of “ well ” is approximately an isotherm R trench = R wall + R surface R bulk = R isolation + R substrate

RLCarter: Analog IC Design with Self Heating25 DIBJT Rth Model

RLCarter: Analog IC Design with Self Heating26 Analogy Modeling of Device Thermal Resistance

RLCarter: Analog IC Design with Self Heating27 Analog IC Design with Self-Heating Heat Source/Temperature Effects Thermal Equations/Analogy Thermal Resistance Models Effect of Thermal Resistance on Device Biasing Effect of Thermal Resistance on the Circuit Performance Conclusions/Future Work

RLCarter: Analog IC Design with Self Heating28 Transient Analysis of a BJT with Multiple Thermal Paths Simulation circuit The thermal network consists of 3 poles  1 =1us,  2 =100us and  3 =10ms Spectre  is used as a simulator

RLCarter: Analog IC Design with Self Heating29 VBIC Model Parameters used for the BJT * Mapped from GP model

RLCarter: Analog IC Design with Self Heating30 Transient Thermal Response - JI BJT 11 22 33

RLCarter: Analog IC Design with Self Heating31 Transient Thermal Response - DIBJT R TH,epi =394 K/W C TH,epi =79.4p sW/K (  epi =31.3ns ) R TH,ox =2742 K/W C TH,ox =39.75p sW/K (  ox =109ns ) R TH,w =126 K/W C TH,w =11.9p sW/K (  w =1.5ms )  epi  ox ww

RLCarter: Analog IC Design with Self Heating32 Build SDD BJT model in ADS SDD (Symbolic Defined Device) Combination of the classical GP model and the thermal network For static model, IS, BF, BR, ISE and ISC values changed by temperature rise

RLCarter: Analog IC Design with Self Heating33 SDD Model verification I B =25uA I B =50uA I B =75uA I B =100uA

RLCarter: Analog IC Design with Self Heating34 Current Mirror Driving BJT with 3 Emitter Fingers Simulation Circuit The multiple finger BJT consists of 3 fingers, Q 1, Q 2 and Q 3. They have the same geometrical size with Q ref Q 2 is the inner finger Thermal coupling occurs between 3 fingers. The coupling factor is C me and C ee No thermal coupling between the multiply finger BJT and Q ref I C1 I C2 I C3 c me c ee

RLCarter: Analog IC Design with Self Heating35 VCVS Thermal Coupling Model

RLCarter: Analog IC Design with Self Heating36 Model Parameters * Typical values for 1um  2um device

RLCarter: Analog IC Design with Self Heating37 Current Ratio (I C /I ref ) for Different R TH 0.051c ee 0.102c me 3umS 2umL 1umW 1um  2um device

RLCarter: Analog IC Design with Self Heating38 Temperature Rise for Different R TH 0.051c ee 0.102c me 3umS 2umL 1umW 1um  2um device

RLCarter: Analog IC Design with Self Heating39 Current Ratio for Different Spacing um um um C ee C me RTH=3000 K/W 5um 7um 3um L=2um W=1um

RLCarter: Analog IC Design with Self Heating40 Temperature Rise for Different Spacing um um um C ee C me R TH =3000 K/W 5um 7um 3um L=2um W=1um

RLCarter: Analog IC Design with Self Heating41 Current Ratio (I C /I ref ) for Different R TH 0.050c ee 0.100c me 3umS 5umL 1umW 1um  5um device

RLCarter: Analog IC Design with Self Heating42 Temperature Rise for Different R TH 0.050c ee 0.100c me 3umS 5umL 1umW 1um  5um device

RLCarter: Analog IC Design with Self Heating43 Current Ratio for Different Spacing um um um C ee C me R TH =2000 K/W 5um 7um 3um L=5um W=1um

RLCarter: Analog IC Design with Self Heating44 Temperature Rise for Different Spacing R TH =2000 K/W L=5um W=1um 5um 7um 3um um um um C ee C me

RLCarter: Analog IC Design with Self Heating45 Analog IC Design with Self-Heating Heat Source/Temperature Effects Thermal Equations/Analogy Thermal Resistance Models Effect of Thermal Resistance on Device Biasing Effect of Thermal Resistance on the Circuit Performance Conclusions/Future Work

RLCarter: Analog IC Design with Self Heating46  A741 Simulation Simulated by Spectre (Ver ) Analog Waveform is used to obtain graphic output Use the circuit posted on WEB ( ee.uta.edu/Online/adavis/analog/f_opamp.cir) Transistor models are mapped to VBIC model using sgp_2_vbic (only one npn and pnp model used) Area of Q 13A is 0.25; Area of Q 13B is 0.75 Areas of Q 14 and Q 20 are 3 Areas of other transistors are 1 Connect  A741 with  15V voltage supplies

RLCarter: Analog IC Design with Self Heating47 μA741 Op-Amp Schematic [1]

RLCarter: Analog IC Design with Self Heating48 Relative Device Temperatures Configure  A741 as a voltage follower DC analysis result R th for all npn transistors is 5000K/W R th for all pnp transistors is 1000KW No load is connected Q 17 is 91 degrees higher than the ambient temperature!

RLCarter: Analog IC Design with Self Heating49 Temperature transitions of Q1 and Q13 (without C th ) Q17Q17 Q 13 (R th,npn =5000 K/W;R th,pnp =1000 K/W)

RLCarter: Analog IC Design with Self Heating50 Temperature transition of Q 17 (1) R th,npn =5000K/W C th,npn =1  sW/K R th,pnp =1000K/W C th,pnp =10  sW/K Need about 60ms to reach the stable temperature

RLCarter: Analog IC Design with Self Heating51 Temperature transition of Q 13 (1) Rth,npn=5000K/W Cth,npn=1  sW/K Rth,pnp=1000K/W Cth,pnp=10  sW/K Need about 60ms to reach the stable temperature

RLCarter: Analog IC Design with Self Heating52 Temperature transition of Q 17 (2) Need about 40ms to reach the stable temperature Temperature var- iation increases R th,npn =5000K/W C th,npn =0.1  sW/K R th,pnp =1000K/W C th,pnp =10  sW/K

RLCarter: Analog IC Design with Self Heating53 Temperature transition of Q 13 (2) Need about 10ms to reach the stable temperature Temperature var- iations increase R th,npn =5000K/W C th,npn =1  sW/K R th,pnp =1000K/W C th,pnp =1  sW/K

RLCarter: Analog IC Design with Self Heating54 Circuit used to measure the open loop gain [2] Use a feedback technique to determine the open loop gain DUT is the op amp to be tested Nulling op amp is connected in a feedback mode R1=100 R2=1M R3=1K Vmid=0 VSRC1 sweeps from 0 to 1V Simulation parameters:

RLCarter: Analog IC Design with Self Heating55 Typical simulation output

RLCarter: Analog IC Design with Self Heating56 Table of open loop gain Note: Each value times 10 4

RLCarter: Analog IC Design with Self Heating57 Surface of open loop gain Interpolation used Decreases about a factor of 60!

RLCarter: Analog IC Design with Self Heating58 Surface of open loop gain (dB view) Decreases about 36dB!

RLCarter: Analog IC Design with Self Heating59 Slew rate (without C th ) Voltage follower is used Input signal 5K pulse input rise and fall time: 1  S Voltage level: 0 and 10V Rising edge is measured Unit: V/  S Only 2% variation

RLCarter: Analog IC Design with Self Heating60 Slew rate (including C th ) Set R th,npn =5000 K/W and R th,pnp =1000 K/W Only 0.4% variation when C th changes Comparing with C th =0 case (0.6751, circled value at previously table), only 1.5% variation Self-heating (isolated) has no significant effect on slew rate

RLCarter: Analog IC Design with Self Heating61 Thermal coupling effect on open-loop gain Use the same circuit discussed previously Set R th,npn =4000 K/W and R th,pnp =900 K/W and C th,npn =C th,pnp =0 The hottest transistor is Q 17 The amplificatory transistors at 1 st stage are Q 3 and Q 4 Temperature node of Q 17 is connected with temperature node of Q 3 and Q 4 by two identical thermal resistors R C

RLCarter: Analog IC Design with Self Heating62 Open-loop gain reduced by thermal coupling Interpolation is used to obtain this curve Decrease about 25.4%!

RLCarter: Analog IC Design with Self Heating63 Analog IC Design with Self-Heating Heat Source/Temperature Effects Thermal Equations/Analogy Thermal Resistance Models Effect of Thermal Resistance on Device Biasing Effect of Thermal Resistance on the Circuit Performance Conclusions/Future Work

RLCarter: Analog IC Design with Self Heating64 Summary VBIC model used to analyze thermal effects Effect of individual device temperatures in a  A741 Inter-device heating effects Isolated self-heating in  A741 Isolated self-heating can reduce the open loop gain Not a significant change in slew rate Preliminary study on thermal coupling effect Open loop gain is reduced if significant thermal coupling exists between 1 st and 2 nd stage Current mirror temperature compensation schemes are more critical when coupling is not optimum.

RLCarter: Analog IC Design with Self Heating65 Acknowledgements: Support TheTexas Higher Education Coordinating Board (THECB) National Semiconductor Corporation (NSC) The National Science Foundation Industry/University Center for Electronic Materials, Devices and Systems (NSF/CEMDAS)

RLCarter: Analog IC Design with Self Heating66 Acknowledgements: Analog IC Research Group Professor W. Alan Davis Zhipeng Zhu Zheng Li Siddharth Nashiney Naveen Kumar Reddy Siddareddygari Shankaranarayanan Rajaraman Piyush Thacker Anurag Lakhlani

RLCarter: Analog IC Design with Self Heating67 References Paul R. Gray, Robert G. Meyer, et al, Analysis and design of analog integrated circuits, New York: Wiley, c2001 Fujiang Lin, et al, “ Extraction Of VBIC Model for SiGe HBTs Made Easy by Going Through Gummel-Poon Model ”, from Avanti Star-spice User Manual, 04, Affirma Spectre Circuit Simulator Device Model Equations Zweidinger, D.T.; Fox, R.M., et al, “ Equivalent circuit modeling of static substrate thermal coupling using VCVS representation ”, Solid-State Circuits, IEEE Journal of, Volume: 2 Issue: 9, Sept. 2002, Page(s): Jonathan S. Brodsky, “Physics based impedance models for the simulation of self-heating in semiconductor devices and circuits”, PhD Dissertation, Dept of Electrical and Computer Engineering, University of Florida, Gainesville, Aug McAndrew, C., Seitchik, J. and etal, ” VBIC95: An improved vertical, IC bipolar transistor model ”, Bipolar/BiCMOS Circuits and Technology Meeting, 1995., Proceedings of the 1995 Burns and Robert, An introduction to mixed-signal testing, Oxford University Press, 1999 Copyright Texas Instruments