Advanced Rendering Technology The AR250 A New Architecture for Ray Traced Rendering.

Slides:



Advertisements
Similar presentations
3D Graphics Content Over OCP Martti Venell Sr. Verification Engineer Bitboys.
Advertisements

1 Copyright © 2012 Oracle and/or its affiliates. All rights reserved. Convergence of HPC, Databases, and Analytics Tirthankar Lahiri Senior Director, Oracle.
Sven Woop Computer Graphics Lab Saarland University
COMPUTER GRAPHICS CS 482 – FALL 2014 NOVEMBER 10, 2014 GRAPHICS HARDWARE GRAPHICS PROCESSING UNITS PARALLELISM.
Computer Abstractions and Technology
Reporter :LYWang We propose a multimedia SoC platform with a crossbar on-chip bus which can reduce the bottleneck of on-chip communication.
TU/e Processor Design 5Z0321 Processor Design 5Z032 Computer Systems Overview Chapter 1 Henk Corporaal Eindhoven University of Technology 2011.
Preparing For Server Installation Instructor: Enoch E. Damson.
THE AMD-K7 TM PROCESSOR Microprocessor Forum 1998 Dirk Meyer.
Khaled A. Al-Utaibi  Computers are Every Where  What is Computer Engineering?  Design Levels  Computer Engineering Fields  What.
Ray-casting in VolumePro™ 1000
CSC457 Seminar YongKang Zhu December 6 th, 2001 About Network Processor.
GRAPHICS AND COMPUTING GPUS Jehan-François Pâris
Computer Graphics Hardware Acceleration for Embedded Level Systems Brian Murray
Room: E-3-31 Phone: Dr Masri Ayob TK 2123 COMPUTER ORGANISATION & ARCHITECTURE Lecture 4: Computer Performance.
3D Graphics Processor Architecture Victor Moya. PhD Project Research on architecture improvements for future Graphic Processor Units (GPUs). Research.
IN4151 Introduction 3D graphics 1 Introduction to 3D computer graphics part 2 Viewing pipeline Multi-processor implementation GPU architecture GPU algorithms.
Parallelizing Raytracing Gillian Smith CMPE 220 February 19 th, 2008.
Pixel Shader Vertex Shader The Real-time Graphics Pipeline Input Assembler Rasterizer Output Merger.
ECE 526 – Network Processing Systems Design
Shading Languages By Markus Kummerer. Markus Kummerer 2 / 19 State of the Art Shading.
PlayStation 2 Architecture Irin Jose Farid Momin Quy Ngo Olivia Wong.
Computer Organization and Assembly language
GPGPU overview. Graphics Processing Unit (GPU) GPU is the chip in computer video cards, PS3, Xbox, etc – Designed to realize the 3D graphics pipeline.
Chipsets and Controllers
Comparison of Next Generation Gaming Architectures Presented By Dela Tsiagbe Presented By Dela Tsiagbe.
Hardware Overview Net+ARM – Well Suited for Embedded Ethernet
Under the Hood: 3D Pipeline. Motherboard & Chipset PCI Express x16.
Computer performance.
Department of Computer Science Southern Illinois University Edwardsville Dr. Hiroshi Fujinoki and Kiran Gollamudi {hfujino,
Xilinx at Work in Hot New Technologies ® Spartan-II 64- and 32-bit PCI Solutions Below ASSP Prices January
Background image by chromosphere.deviantart.com Fella in following slides by devart.deviantart.com DM2336 Programming hardware shaders Dioselin Gonzalez.
RSC Williams MAPLD 2005/BOF-S1 A Linux-based Software Environment for the Reconfigurable Scalable Computing Project John A. Williams 1
UC Berkeley 1 The Datacenter is the Computer David Patterson Director, RAD Lab January, 2007.
February 12, 1998 Aman Sareen DPGA-Coupled Microprocessors Commodity IC’s for the Early 21st Century by Aman Sareen School of Electrical Engineering and.
1 3-General Purpose Processors: Altera Nios II 2 Altera Nios II processor A 32-bit soft core processor from Altera Comes in three cores: Fast, Standard,
Mark Franklin, S06 CS, CoE, EE 362 Digital Computers II: Architecture Prof. Mark Franklin: Course Assistants: –Drew Frank:
Architecture Examples And Hierarchy Samuel Njoroge.
Uncovering the Multicore Processor Bottlenecks Server Design Summit Shay Gal-On Director of Technology, EEMBC.
Advanced Computer Architecture, CSE 520 Generating FPGA-Accelerated DFT Libraries Chi-Li Yu Nov. 13, 2007.
Multiprocessing. Going Multi-core Helps Energy Efficiency William Holt, HOT Chips 2005 Adapted from UC Berkeley "The Beauty and Joy of Computing"
Lecture 1 1 Computer Systems Architecture Lecture 1: What is Computer Architecture?
Introduction to Parallel Rendering Jian Huang, CS 594, Spring 2002.
3/15/2002CSE Final Remarks Concluding Remarks SOAP.
Stream Processing Main References: “Comparing Reyes and OpenGL on a Stream Architecture”, 2002 “Polygon Rendering on a Stream Architecture”, 2000 Department.
1 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Architectures Iowa State University (Ames) Reconfigurable Architectures Forces that drive.
1 by: Ilya Melamed Supervised by: Eyal Sarfati High Speed Digital Systems Lab.
Development of Programmable Architecture for Base-Band Processing S. Leung, A. Postula, Univ. of Queensland, Australia A. Hemani, Royal Institute of Tech.,
Hardware Benchmark Results for An Ultra-High Performance Architecture for Embedded Defense Signal and Image Processing Applications September 29, 2004.
Data Management for Decision Support Session-4 Prof. Bharat Bhasker.
A SEMINAR ON 1 CONTENT 2  The Stream Programming Model  The Stream Programming Model-II  Advantage of Stream Processor  Imagine’s.
GPU Based Sound Simulation and Visualization Torbjorn Loken, Torbjorn Loken, Sergiu M. Dascalu, and Frederick C Harris, Jr. Department of Computer Science.
Playstation2 Architecture Architecture Hardware Design.
From Turing Machine to Global Illumination Chun-Fa Chang National Taiwan Normal University.
Unit 4 Day 1 FOCS – Introduction to Programming. Journal Entry: Unit #5Entry #1 In detail describe programming in Scratch. Describe how to use Events,
Lecture 27 Multiprocessor Scheduling. Last lecture: VMM Two old problems: CPU virtualization and memory virtualization I/O virtualization Today Issues.
WorldScape Defense Company, L.L.C. Company Proprietary Slide 1 An Ultra-High Performance Scalable Processing Architecture for HPC and Embedded Applications.
Ray Tracing by GPU Ming Ouhyoung. Outline Introduction Graphics Hardware Streaming Ray Tracing Discussion.
CDA-5155 Computer Architecture Principles Fall 2000 Multiprocessor Architectures.
CSL 859: Advanced Computer Graphics Dept of Computer Sc. & Engg. IIT Delhi.
SEPTEMBER 8, 2015 Computer Hardware 1-1. HARDWARE TERMS CPU — Central Processing Unit RAM — Random-Access Memory  “random-access” means the CPU can read.
Hardware Architecture
Veysi ISLER, Department of Computer Engineering, Middle East Technical University, Ankara, TURKEY Spring
Petri Nordlund Chief Architect Bitboys Oy
CMSC 611: Advanced Computer Architecture
Petri Nordlund Chief Architect Bitboys Oy
CS775: Computer Architecture
Introduction to Heterogeneous Parallel Computing
Computer Evolution and Performance
RADEON™ 9700 Architecture and 3D Performance
Presentation transcript:

Advanced Rendering Technology The AR250 A New Architecture for Ray Traced Rendering

Advanced Rendering Technology SIGGRAPH ‘99 – Slides Architecture overview AR250 Rendering Processor RenderDrive Network Appliance How and why it works Problems with Parallelism The ART Model Main AR250 Data Flows AR250 Statistics Analysis Performance Functionality Rendering Speed

Advanced Rendering Technology AR250 Rendering Processor Host Bus Interface Host Bus Interface Ray Tracing Engine Ray Tracing Engine Control Unit Control Unit Memory Manager Memory Manager On Chip Data Cache On Chip Data Cache Host System PCI Interface Additional AR250 processors Local DRAM

Advanced Rendering Technology RenderDrive Network Appliance CPU / Motherboard Flash memory boot disk AR250s x 16 Embedded OS RenderMan compliant renderer Compressed RenderMan protocol HTML job control TCP / IP LAN RenderDrive Web Server 3D Workstation RenderPipe Internet Images 3D Application RenderGate

Advanced Rendering Technology Problems with Parallelism Data distribution Load balancing Scalability of calculation Complexity

Advanced Rendering Technology The ART Model Hardware intersection pipeline Ray-parallel data distribution Broadcast parallelism of geometry Hierarchical geometry Distributed concurrent shading Vector parallel programmable shading acceleration

Advanced Rendering Technology Main AR250 Data Flows Host bus interface Pipeline-parallel ray geometry engine (permutes multiple geometry and rays) Pipeline-parallel ray geometry engine (permutes multiple geometry and rays) Programmable shading co-processor Programmable shading co-processor On-chip data caches On-chip data caches Host system interface Geometry Rays Ray generation & control (CPU) Ray generation & control (CPU) Geometry and shaders (broadcast) Pixels (sequential read-back) Additional AR250 processors Intersections Geometry & shaders Shader ops. Pixels Fine grain distribution of rays between AR250s for load balancing Hierarchical geometry Programmable shaders DRAM

Advanced Rendering Technology AR250 Statistics 0.35um drawn, LSI Logic G10 silicon process 650K gates, 106mm 2 die Custom RISC processor core 32, single-stage, 32 bit IEEE compatible floating-point units Multi-dimensional noise, square root and trig. functions 50 MHz operation

Advanced Rendering Technology Analysis Load balancing through fine-grain parallelism Efficient data distribution by caching rays locally and broadcasting geometry Scalability by performing whole rendering calculation, including shading. Low complexity programming model by support for programmable shading in silicon

Advanced Rendering Technology Functionality Current Full shading model Full ray-traced: Camera motion blur Depth of field Area lights Volumes Planned Global illumination Completion of RenderMan support

Advanced Rendering Technology Rendering Speed Hebe mirror (1322 x 2000) RenderDrive (16 x AR250) 0 hrs 13 min 2 sec BMRT (PII - 333) 22 hrs 8 min Speed  C x P 0.82