By Chad Andrus

TILE-Gx100  100 Identical Processor Cores Each core has its own L2 & L3 cache Each can run its own OS or group together for multiprocessing Cores can be dedicated to specific applications  Targeted to run Performance Applications

Specs  1.5GHz per tile  256K L2 cache per tile  750 billion operations per second  500 Gbps memory bandwidth  200 Tbps of on-chip mesh interconnect (iMesh) "Think of it as the Internet on a chip“ - Bob Doud

What is iMesh?  Five different layers: Memory Input/Output Cache coherency User Space (2)  Tile system allows each core to interact with every other core

Benefits  Reduce costs – can eliminate dozens of computing systems  Efficiency - processing resources can be specifically allocated Optimize performance, save power  Fast computing

Sources  processor-announced-tilera.htm processor-announced-tilera.htm   Cores-Into-Next-Gen-Processors html Cores-Into-Next-Gen-Processors html