1. Interacting Finite State Machine Design Shaun Murphy

2. Problem Statement If transmitter is not busy: the processor sets the data to be transmitted on a data bus and sends a signal to the transmitter to load the data and begin the transmission sequence Once the transmitter has begun transferring the signal, it sets busy and no longer receives data from the processor

3. Problem Statement (Con’t) The receiver should be implemented dependant on a software defined clock divided window When a generated clock signal is created, the receiver’s lines are loaded. Realization should not include propagation delays.

4. State Diagrams

5. Timing Transmitter

6. Timing Receiver

7. Multiple (Interacting) Processes Since a process statement is a concurrent statement, it is possible to have more than one process within an architecture body. This makes interacting finite state machines easy to implement. Processes communicate with each other using signals public to all processes. Variables declared within a process are not visible outside.

8. Behavioral Modeling The behavior of the entity is expressed using sequentially executed, procedural code. A process statement is the primary mechanism used to model the behavior of the entity. Every entity represented using an entity declaration and at least one architecture body.

9. Transmitter States entity FSM1 is port (CLOCK:in); port (CLOCK:in); end FSM1; architecture TRANSMIT of FSM1 is type MP_STATE_TYPE is (M1,M2,M3); type MP_STATE_TYPE is (M1,M2,M3); type TX_STATE_TYPE is (T1,T2,T3,T4); type TX_STATE_TYPE is (T1,T2,T3,T4); signal MP_STATE: MP_STATE_TYPE; signal MP_STATE: MP_STATE_TYPE; signal TX_STATE: TX_STATE_TYPE; signal TX_STATE: TX_STATE_TYPE; signal LOAD_TX, TX_BUSY: BIT; signal LOAD_TX, TX_BUSY: BIT; -- Entity declarations are the ‘black-box’ view -- Clock is an input signal -- Internal view of the entity -- Enumeration types -- Signal declarations -- MP_STATE is of type MP_STATE_TYPE -- Initial (left most) value of BIT is ‘0’

10. Transmitter Process Statements begin MP: process MP: process begin begin wait until CLOCK='0'; wait until CLOCK='0'; case MP_STATE is case MP_STATE is -- load data -- load data when M1 => when M1 => LOAD_TX <='1'; LOAD_TX <='1'; MP_STATE <=M2; MP_STATE <=M2; when M2 => when M2 => if TX_BUSY ='1' then if TX_BUSY ='1' then LOAD_TX <='0'; LOAD_TX <='0'; MP_STATE <=M3; MP_STATE <=M3; end if; end if; -- wait for TX to complete -- wait for TX to complete when M3 => when M3 => if TX_BUSY ='0' then if TX_BUSY ='0' then MP_STATE <=M1; MP_STATE <=M1; end if; end if; end case; end case; end process MP; end process MP; -- Process statements contain sequential statements -- First way to be sensitive to a falling edge event -- Signal assignment statement (no delay) -- Since these occur inside a process, sequential

11. TX: process (CLOCK) TX: process (CLOCK) begin begin if CLOCK='0' then if CLOCK='0' then case TX_STATE is case TX_STATE is -- wait for load data -- wait for load data when T1 => when T1 => if LOAD_TX ='1' then if LOAD_TX ='1' then TX_STATE <=T2; TX_STATE <=T2; -- read data -- read data TX_BUSY <='1'; TX_BUSY <='1'; end if; end if; -- transmitting data -- transmitting data when T2 => when T2 => TX_STATE <=T3; TX_STATE <=T3; when T3 => when T3 => TX_STATE <=T4; TX_STATE <=T4; -- transmission complete -- transmission complete when T4 => when T4 => TX_BUSY <='0' TX_BUSY <='0' TX_STATE <=T1; TX_STATE <=T1; end case; end case; end if; end if; end process TX; end process TX; end TRANSMIT; -- TX is sensitive on a CLOCK event (second method) -- Check to see if this is falling edge -- Select appropriate branch for execution. -- process suspends until another clock event

12. Receiver Source architecture RECEIVER of FSM2 is type DIV_STATE_TYPE is (D1,D2,D3); type DIV_STATE_TYPE is (D1,D2,D3); type RX_STATE_TYPE is (R1,R2); type RX_STATE_TYPE is (R1,R2); signal DIV_STATE: DIV_STATE_TYPE; signal DIV_STATE: DIV_STATE_TYPE; signal RX_STATE: RX_STATE_TYPE; signal RX_STATE: RX_STATE_TYPE; signal NEW_CLOCK: BIT; signal NEW_CLOCK: BIT; -- Signal CLOCK is an input port. -- Signal CLOCK is an input port. -- new architecture for a different entity -- enumeration types

13. Receiver Process Statements begin DIVIDER: process DIVIDER: process begin begin wait until CLOCK='1' wait until CLOCK='1' case DIV_STATE is case DIV_STATE is when D1 => DIV_STATE DIV_STATE <= D2; NEW_CLOCK <='0‘; when D2 => DIV_STATE DIV_STATE <= D3; when D3 => NEW_CLOCK NEW_CLOCK <='1'; DIV_STATE <=D1; end case; end case; end process DIVIDER; end process DIVIDER; RX: process RX: process begin begin wait until NEW_CLOCK ='0'; wait until NEW_CLOCK ='0'; case RX_STATE is case RX_STATE is when R1 => RX_STATE RX_STATE <=R2; when R2 => RX_STATE RX_STATE <=R1; end case; end case; end process RX; end process RX; end architecture RECEIVER; -- new process -- this process waits for a rising edge -- this process waits for the trailing edge on the new clock -- the receiver simply changes state. In the real system, the receiver would have some READ_WORD procedure