1. Self-Tuned Distributed Multiprocessor System Xiaoyan Bi CSC8410 - Operating Systems Dr. Mirela Damian

2. Motivation With massively parallel computing architectures are becoming widely accepted in many computationally intensive areas, we met some problems with scaling these machines to larger and larger configurations:  The nature of the interconnection network  All the nodes have to be of the same type

3. Features of Synchronous & Asynchronous systems  Synchronous systems rely on faith Disadvantage: the enormous difference between best case and worst case timing in synchronous components  Asynchronous system rely on measurement Disadvantage: the round-trip signaling are done sequentially, and this slows the system down considerably.  Conclusion: small synchronous circuits are inherently faster than self-timed circuits.

4. Overview  Definition  Advantages  Measurement in Self-Tuned Systems  Nodes  Interconnection Network Topology

5. Self-tuning, a technique devised by Ted Kehl, is a new clocking paradigm which incorporates the best features of conventional synchronous logic along with advantages offered by the asynchronous, self-timed paradigm. What is Self-Tuning?

6. Measurement  Self-tuning makes the measurements as in asynchronous systems but defers any correction of the clock to future cycles.  Measurement takes place by looking for transitions in the data.  Measurement strategy

7. Advantages of Self-Tuned Systems  Never needs to know the actual operating speed of the circuit.  Not only guaranteed to operate at close to the circuitry’s actual operating speed, but also expect increased robustness.

8. Nodes -- The basic node in the architecture is a combined processor-memory-switching element.

9.  Processor Unit It is a device which can generate addresses and data and accept data it may have requested.  Memory Unit It typically will comprise a memory array, associated error detection and correction and control logic, and a controlling device.  External Communications Interfaces Communication between nodes.  Switching The switching component has been distributed equally across all nodes and is a moderate overhead on each board. Nodes

10. Interconnection Network Topology  Planar Topology with 4 Nodes per Bus  Cylindrical Topology with 4 Nodes per Bus  Spherical Topology with 4 Nodes per Bus  Topologies with 6 Nodes per Bus  Another Dimension

11. Demo

12. Topologies with 6 Nodes per Bus

13. Conclusion Self-Tuned Distributed Multiprocessor System is a non- uniform memory access, distributed memory multiprocessor system. It has superior properties with regard to incremental scalability compared with most competing systems. Attention to engineering considerations has led to an economical system with great commercial potential.

14. Questions?