1. EE2174: Digital Logic and Lab Professor Shiyan Hu Department of Electrical and Computer Engineering Michigan Technological University CHAPTER 3 Combinational Logic

2. 1-Mar-16 PJF - 2Chapter 2-i: Combinational Logic Circuits (2.1-- 2.5)Overview Binary logic and Gates Binary logic and Gates Boolean Algebra Boolean Algebra Basic Properties Basic Properties Algebraic Manipulation Algebraic Manipulation Standard and Canonical Forms Standard and Canonical Forms Minterms and Maxterms (Canonical forms) Minterms and Maxterms (Canonical forms) SOP and POS (Standard forms) SOP and POS (Standard forms) Karnaugh Maps (K-Maps) Karnaugh Maps (K-Maps) 2, 3, 4, and 5 variable maps 2, 3, 4, and 5 variable maps Simplification using K-Maps Simplification using K-Maps K-Map Manipulation K-Map Manipulation Implicants: Prime, Essential Implicants: Prime, Essential Don’t Cares Don’t Cares

3. 1-Mar-16 PJF - 3Chapter 2-i: Combinational Logic Circuits (2.1-- 2.5) Binary Logic Deals with binary variables that take 2 discrete values (0 and 1), and with logic operations Deals with binary variables that take 2 discrete values (0 and 1), and with logic operations Three basic logic operations: Three basic logic operations: AND, OR, NOT AND, OR, NOT Binary/logic variables are typically represented as letters: A,B,C,…,X,Y,Z Binary/logic variables are typically represented as letters: A,B,C,…,X,Y,Z

4. 1-Mar-16 PJF - 4Chapter 2-i: Combinational Logic Circuits (2.1-- 2.5) Binary Logic Function F(vars) = expression Example: F(a,b) = a’b + b’ G(x,y,z) = x(y+z’) set of binary variables Operators ( +,, ‘ ) Operators ( +,, ‘ ) Variables Variables Constants ( 0, 1 ) Constants ( 0, 1 ) Groupings (parenthesis) Groupings (parenthesis)

5. 1-Mar-16 PJF - 5Chapter 2-i: Combinational Logic Circuits (2.1-- 2.5) Basic Logic Operators AND (also, ) AND (also, ) OR (also +, ) OR (also +, ) NOT (also ’, ) NOT (also ’, ) F(a,b) = ab, reads F is 1 if and only if a=b=1 F(a,b) = ab, reads F is 1 if and only if a=b=1 G(a,b) = a+b, reads G is 1 if either a=1 or b=1 G(a,b) = a+b, reads G is 1 if either a=1 or b=1 H(a) = a’, reads H is 1 if a=0 H(a) = a’, reads H is 1 if a=0 Binary Unary

6. 1-Mar-16 PJF - 6Chapter 2-i: Combinational Logic Circuits (2.1-- 2.5) Basic Logic Operators (cont.) 1-bit logic AND resembles binary multiplication: 1-bit logic AND resembles binary multiplication: 0 0 = 0,0 1 = 0, 1 0 = 0,1 1 = 1 1-bit logic OR resembles binary addition, except for one operation: 1-bit logic OR resembles binary addition, except for one operation: 0 + 0 = 0,0 + 1 = 1, 1 + 0 = 1,1 + 1 = 1 (≠ 10 2 ) 1 + 0 = 1,1 + 1 = 1 (≠ 10 2 )

7. 1-Mar-16 PJF - 7Chapter 2-i: Combinational Logic Circuits (2.1-- 2.5) Truth Tables for logic operators Truth table: tabular form that uniquely represents the relationship between the input variables of a function and its output AB F=AB 00 0 01 0 10 0 11 1 2-Input ANDAB F=A+B 00 0 01 1 10 1 11 1 2-Input ORA F=A’ 0 1 1 0 NOT

8. 1-Mar-16 PJF - 8Chapter 2-i: Combinational Logic Circuits (2.1-- 2.5) Truth Tables (cont.) Q: Let a function F() depend on n variables. How many rows are there in the truth table of F() ? Q: Let a function F() depend on n variables. How many rows are there in the truth table of F() ? A: A: 2 n rows, since there are 2 n possible binary patterns/combinations for the n variables

9. 1-Mar-16 PJF - 9Chapter 2-i: Combinational Logic Circuits (2.1-- 2.5) Logic Gates Logic gates are abstractions of electronic circuit components that operate on one or more input signals to produce an output signal. Logic gates are abstractions of electronic circuit components that operate on one or more input signals to produce an output signal. 2-Input AND 2-Input ORNOT (Inverter) A A A B B FGH F = AB G = A+B H = A’

10. 1-Mar-16 PJF - 10Chapter 2-i: Combinational Logic Circuits (2.1-- 2.5) Timing Diagram A B F=A B + G=A + B H=A’ 1 1 1 1 1 0 0 0 0 0 t0t0 t1t1 t2t2 t3t3 t4t4 t5t5 t6t6 Input signals Gate Output Signals Basic Assumption: Zero time for signals to propagate Through gates Transitions

11. 1-Mar-16 PJF - 11Chapter 2-i: Combinational Logic Circuits (2.1-- 2.5) Combinational Logic Circuit from Logic Function Consider function F = A’ + BC’ + A’B’ Consider function F = A’ + BC’ + A’B’ A combinational logic circuit can be constructed to implement F, by appropriately connecting input signals and logic gates: A combinational logic circuit can be constructed to implement F, by appropriately connecting input signals and logic gates: Circuit input signals  from function variables (A, B, C) Circuit input signals  from function variables (A, B, C) Circuit output signal  function output (F) Circuit output signal  function output (F) Logic gates  from logic operations Logic gates  from logic operations A B C F

12. 1-Mar-16 PJF - 12Chapter 2-i: Combinational Logic Circuits (2.1-- 2.5) Combinational Logic Circuit from Logic Function (cont.) In order to design a cost- effective and efficient circuit, we must minimize the circuit’s size (area) and propagation delay (time required for an input signal change to be observed at the output line) In order to design a cost- effective and efficient circuit, we must minimize the circuit’s size (area) and propagation delay (time required for an input signal change to be observed at the output line) Observe the truth table of F=A’ + BC’ + A’B’ and G=A’ + BC’ Observe the truth table of F=A’ + BC’ + A’B’ and G=A’ + BC’ Truth tables for F and G are identical  same function Truth tables for F and G are identical  same function Use G to implement the logic circuit (less components) Use G to implement the logic circuit (less components) ABCFG 0 0 0 1 1 0 0 1 1 1 0 1 0 1 1 0 1 1 1 1 1 0 0 0 0 1 0 1 0 0 1 1 0 1 1 1 1 1 0 0

13. 1-Mar-16 PJF - 13Chapter 2-i: Combinational Logic Circuits (2.1-- 2.5) Combinational Logic Circuit from Logic Function (cont.) A B C F A B C G

14. 1-Mar-16 PJF - 14Chapter 2-i: Combinational Logic Circuits (2.1-- 2.5) Boolean Algebra VERY nice machinery used to manipulate (simplify) Boolean functions VERY nice machinery used to manipulate (simplify) Boolean functions George Boole (1815-1864): “An investigation of the laws of thought” George Boole (1815-1864): “An investigation of the laws of thought” Terminology: Terminology: Literal: A variable or its complement Literal: A variable or its complement Product term: literals connected by Product term: literals connected by Sum term: literals connected by + Sum term: literals connected by +

15. 1-Mar-16 PJF - 15Chapter 2-i: Combinational Logic Circuits (2.1-- 2.5) Boolean Algebra Properties Let X: boolean variable, 0,1: constants 1. X + 0 = X -- Zero Axiom 2. X 1 = X -- Unit Axiom 3. X + 1 = 1 -- Unit Property 4. X 0 = 0 -- Zero Property

16. 1-Mar-16 PJF - 16Chapter 2-i: Combinational Logic Circuits (2.1-- 2.5) Boolean Algebra Properties (cont.) Let X: boolean variable, 0,1: constants 5. X + X = X -- Idepotence 6. X X = X -- Idepotence 7. X + X’ = 1 -- Complement 8. X X’ = 0 -- Complement 9. (X’)’ = X-- Involution

17. 1-Mar-16 PJF - 17Chapter 2-i: Combinational Logic Circuits (2.1-- 2.5) The Duality Principle The dual of an expression is obtained by exchanging ( and +), and (1 and 0) in it, provided that the precedence of operations is not changed. The dual of an expression is obtained by exchanging ( and +), and (1 and 0) in it, provided that the precedence of operations is not changed. Cannot exchange x with x’ Cannot exchange x with x’ Example: Example: Find H(x,y,z), the dual of F(x,y,z) = x’yz’ + x’y’z Find H(x,y,z), the dual of F(x,y,z) = x’yz’ + x’y’z H = (x’+y+z’) (x’+y’+ z) H = (x’+y+z’) (x’+y’+ z)

18. 1-Mar-16 PJF - 18Chapter 2-i: Combinational Logic Circuits (2.1-- 2.5) The Duality Principle (cont.) With respect to duality, Identities 1 – 8 have the following relationship: 1. X + 0 = X 2. X 1 = X (dual of 1 ) 3. X + 1 = 1 4. X 0 = 0 (dual of 3 ) 5. X + X = X 6. X X = X (dual of 5 ) 7. X + X’ = 1 8. X X’ = 0 (dual of 8 )

19. 1-Mar-16 PJF - 19Chapter 2-i: Combinational Logic Circuits (2.1-- 2.5) More Boolean Algebra Properties Let X,Y, and Z: boolean variables 10. X + Y = Y + X 11. X Y = Y X -- Commutative 12. X + (Y+Z) = (X+Y) + Z 13. X(YZ) = (XY)Z -- Associative 14. X(Y+Z) = XY + XZ 15. X+(YZ) = (X+Y) (X+Z) -- Distributive 16. ( X + Y)’ = X’ Y’ 17. ( X Y)’ = X’ + Y’ -- DeMorgan’s In general, In general, ( X 1 + X 2 + … + X n )’ = X 1 ’X 2 ’ … X n ’, and ( X 1X 2… X n )’ = X 1 ’ + X 2 ’ + … + X n ’

20. 1-Mar-16 PJF - 20Chapter 2-i: Combinational Logic Circuits (2.1-- 2.5) Absorption Property (Covering) Absorption Property (Covering) 1. x + xy = x 2. x(x+y) = x (dual) Proof: x + xy = x1 + xy = x(1+y) = x1 = x QED (2 true by duality, why?) Proof: x + xy = x1 + xy = x(1+y) = x1 = x QED (2 true by duality, why?)

21. 1-Mar-16 PJF - 21Chapter 2-i: Combinational Logic Circuits (2.1-- 2.5) Power of Duality Power of Duality 1. x + xy = x is true, so (x + xy)’=x’ 2. (x + xy)’=x’(x’+y’) 3. x’(x’+y’) =x’ 4. Let X=x’, Y=y’ 5. X(X+Y) =X, which is the dual of x + xy = x. 6. The above process can be applied to any formula. So if a formula is valid, then its dual must also be valid. 7. Proving one formula also proves its dual

22. 1-Mar-16 PJF - 22Chapter 2-i: Combinational Logic Circuits (2.1-- 2.5) Consensus Theorem 1. xy + x’z + yz = xy + x’z 2. (x+y)(x’+z)(y+z) = (x+y)(x’+z) -- (dual) Proof: xy + x’z + yz = xy + x’z + (x+x’)yz = xy + x’z + xyz + x’yz = (xy + xyz) + (x’z + x’zy) = xy + x’z QED (2 true by duality). Proof: xy + x’z + yz = xy + x’z + (x+x’)yz = xy + x’z + xyz + x’yz = (xy + xyz) + (x’z + x’zy) = xy + x’z QED (2 true by duality).

23. 1-Mar-16 PJF - 23Chapter 2-i: Combinational Logic Circuits (2.1-- 2.5) Truth Tables (revisited) Enumerates all possible combinations of variable values and the corresponding function value Enumerates all possible combinations of variable values and the corresponding function value Truth tables for some arbitrary functions F 1 (x,y,z), F 2 (x,y,z), and F 3 (x,y,z) are shown to the right. Truth tables for some arbitrary functions F 1 (x,y,z), F 2 (x,y,z), and F 3 (x,y,z) are shown to the right. xyz F1F1F1F1 F2F2F2F2 F3F3F3F3 000011 001001 010001 011011 100010 101010 110000 111101

24. 1-Mar-16 PJF - 24Chapter 2-i: Combinational Logic Circuits (2.1-- 2.5) Truth Tables (cont.) Truth table: a unique representation of a Boolean function Truth table: a unique representation of a Boolean function If two functions have identical truth tables, the functions are equivalent (and vice-versa). If two functions have identical truth tables, the functions are equivalent (and vice-versa). Truth tables can be used to prove equality theorems. Truth tables can be used to prove equality theorems. However, the size of a truth table grows exponentially with the number of variables involved, hence unwieldy. This motivates the use of Boolean Algebra. However, the size of a truth table grows exponentially with the number of variables involved, hence unwieldy. This motivates the use of Boolean Algebra.

25. 1-Mar-16 PJF - 25Chapter 2-i: Combinational Logic Circuits (2.1-- 2.5) Boolean expressions-NOT unique Unlike truth tables, expressions representing a Boolean function are NOT unique. Unlike truth tables, expressions representing a Boolean function are NOT unique. Example: Example: F(x,y,z) = x’y’z’ + x’yz’ + xyz’ F(x,y,z) = x’y’z’ + x’yz’ + xyz’ G(x,y,z) = x’y’z’ + yz’ G(x,y,z) = x’y’z’ + yz’ The corresponding truth tables for F() and G() are to the right. They are identical! The corresponding truth tables for F() and G() are to the right. They are identical! Thus, F() = G() Thus, F() = G() xyzFG 00011 00100 01011 01100 10000 10100 11011 11100

26. 1-Mar-16 PJF - 26Chapter 2-i: Combinational Logic Circuits (2.1-- 2.5) Algebraic Manipulation Boolean algebra is a useful tool for simplifying digital circuits. Boolean algebra is a useful tool for simplifying digital circuits. Why do it? Simpler can mean cheaper, smaller, faster (revisit slides 11-13). Why do it? Simpler can mean cheaper, smaller, faster (revisit slides 11-13). Example: Simplify F = x’yz + x’yz’ + xz. F= x’yz + x’yz’ + xz = x’y(z+z’) + xz = x’y1 + xz = x’y + xz Example: Simplify F = x’yz + x’yz’ + xz. F= x’yz + x’yz’ + xz = x’y(z+z’) + xz = x’y1 + xz = x’y + xz

27. 1-Mar-16 PJF - 27Chapter 2-i: Combinational Logic Circuits (2.1-- 2.5) Algebraic Manipulation (cont.) Example: Prove x’y’z’ + x’yz’ + xyz’ = x’z’ + yz’ Example: Prove x’y’z’ + x’yz’ + xyz’ = x’z’ + yz’ Proof: x’y’z’+ x’yz’+ xyz’ = x’y’z’ + x’yz’ + x’yz’ + xyz’ = x’z’(y’+y) + yz’(x’+x) = x’z’1 + yz’1 = x’z’ + yz’ QED. Proof: x’y’z’+ x’yz’+ xyz’ = x’y’z’ + x’yz’ + x’yz’ + xyz’ = x’z’(y’+y) + yz’(x’+x) = x’z’1 + yz’1 = x’z’ + yz’ QED.

28. 1-Mar-16 PJF - 28Chapter 2-i: Combinational Logic Circuits (2.1-- 2.5) Complement of a Function The complement of a function is derived by interchanging ( and +), and (1 and 0), and complementing each variable. The complement of a function is derived by interchanging ( and +), and (1 and 0), and complementing each variable. Otherwise, interchange 1s to 0s in the truth table column showing F. Otherwise, interchange 1s to 0s in the truth table column showing F. The complement of a function IS NOT THE SAME as the dual of a function. The complement of a function IS NOT THE SAME as the dual of a function.

29. 1-Mar-16 PJF - 29Chapter 2-i: Combinational Logic Circuits (2.1-- 2.5) Complementation: Example Find G(x,y,z), the complement of F(x,y,z) = xy’z’ + x’yz Find G(x,y,z), the complement of F(x,y,z) = xy’z’ + x’yz G = F’ = (xy’z’ + x’yz)’ = (xy’z’)’ (x’yz)’ DeMorgan = (x’+y+z) (x+y’+z’) DeMorgan again G = F’ = (xy’z’ + x’yz)’ = (xy’z’)’ (x’yz)’ DeMorgan = (x’+y+z) (x+y’+z’) DeMorgan again Note: The complement of a function can also be derived by finding the function’s dual, and then complementing all of the literals Note: The complement of a function can also be derived by finding the function’s dual, and then complementing all of the literals

30. 1-Mar-16 PJF - 30Chapter 2-i: Combinational Logic Circuits (2.1-- 2.5) Canonical and Standard Forms We need to consider formal techniques for the simplification of Boolean functions. We need to consider formal techniques for the simplification of Boolean functions. Minterms and Maxterms Minterms and Maxterms Sum-of-Minterms and Product-of- Maxterms Sum-of-Minterms and Product-of- Maxterms Product and Sum terms Product and Sum terms Sum-of-Products (SOP) and Product-of-Sums (POS) Sum-of-Products (SOP) and Product-of-Sums (POS)

31. 1-Mar-16 PJF - 31Chapter 2-i: Combinational Logic Circuits (2.1-- 2.5) Definitions Literal: A variable or its complement Literal: A variable or its complement Product term: literals connected by Product term: literals connected by Sum term: literals connected by + Sum term: literals connected by + Minterm: a product term in which all the variables appear exactly once, either complemented or uncomplemented Minterm: a product term in which all the variables appear exactly once, either complemented or uncomplemented Maxterm: a sum term in which all the variables appear exactly once, either complemented or uncomplemented Maxterm: a sum term in which all the variables appear exactly once, either complemented or uncomplemented

32. 1-Mar-16 PJF - 32Chapter 2-i: Combinational Logic Circuits (2.1-- 2.5) Minterm Represents exactly one combination in the truth table. Represents exactly one combination in the truth table. Denoted by m j, where j is the decimal equivalent of the minterm’s corresponding binary combination (b j ). Denoted by m j, where j is the decimal equivalent of the minterm’s corresponding binary combination (b j ). A variable in m j is complemented if its value in b j is 0, otherwise is uncomplemented. A variable in m j is complemented if its value in b j is 0, otherwise is uncomplemented. Example: Assume 3 variables (A,B,C), and j=3. Then, b j = 011 and its corresponding minterm is denoted by m j = A’BC Example: Assume 3 variables (A,B,C), and j=3. Then, b j = 011 and its corresponding minterm is denoted by m j = A’BC

33. 1-Mar-16 PJF - 33Chapter 2-i: Combinational Logic Circuits (2.1-- 2.5) Maxterm Represents exactly one combination in the truth table. Represents exactly one combination in the truth table. Denoted by M j, where j is the decimal equivalent of the maxterm’s corresponding binary combination (b j ). Denoted by M j, where j is the decimal equivalent of the maxterm’s corresponding binary combination (b j ). A variable in M j is complemented if its value in b j is 1, otherwise is uncomplemented. A variable in M j is complemented if its value in b j is 1, otherwise is uncomplemented. Example: Assume 3 variables (A,B,C), and j=3. Then, b j = 011 and its corresponding maxterm is denoted by M j = A+B’+C’ Example: Assume 3 variables (A,B,C), and j=3. Then, b j = 011 and its corresponding maxterm is denoted by M j = A+B’+C’

34. 1-Mar-16 PJF - 34Chapter 2-i: Combinational Logic Circuits (2.1-- 2.5) Truth Table notation for Minterms and Maxterms Minterms and Maxterms are easy to denote using a truth table. Minterms and Maxterms are easy to denote using a truth table. Example: Assume 3 variables x,y,z (order is fixed) Example: Assume 3 variables x,y,z (order is fixed) xyzMintermMaxterm 000 x’y’z’ = m 0 x+y+z = M 0 001 x’y’z = m 1 x+y+z’ = M 1 010 x’yz’ = m 2 x+y’+z = M 2 011 x’yz = m 3 x+y’+z’= M 3 100 xy’z’ = m 4 x’+y+z = M 4 101 xy’z = m 5 x’+y+z’ = M 5 110 xyz’ = m 6 x’+y’+z = M 6 111 xyz = m 7 x’+y’+z’ = M 7

35. 1-Mar-16 PJF - 35Chapter 2-i: Combinational Logic Circuits (2.1-- 2.5) Canonical Forms (Unique) Any Boolean function F( ) can be expressed as a unique sum of minterms and a unique product of maxterms (under a fixed variable ordering). Any Boolean function F( ) can be expressed as a unique sum of minterms and a unique product of maxterms (under a fixed variable ordering). In other words, every function F() has two canonical forms: In other words, every function F() has two canonical forms: Canonical Sum-Of-Products (sum of minterms) Canonical Sum-Of-Products (sum of minterms) Canonical Product-Of-Sums(product of maxterms) Canonical Product-Of-Sums(product of maxterms)

36. 1-Mar-16 PJF - 36Chapter 2-i: Combinational Logic Circuits (2.1-- 2.5) Canonical Forms (cont.) Canonical Sum-Of-Products: The minterms included are those m j such that F( ) = 1 in row j of the truth table for F( ). Canonical Sum-Of-Products: The minterms included are those m j such that F( ) = 1 in row j of the truth table for F( ). Canonical Product-Of-Sums: The maxterms included are those M j such that F( ) = 0 in row j of the truth table for F( ). Canonical Product-Of-Sums: The maxterms included are those M j such that F( ) = 0 in row j of the truth table for F( ).

37. 1-Mar-16 PJF - 37Chapter 2-i: Combinational Logic Circuits (2.1-- 2.5) Example Truth table for f 1 (a,b,c) at right Truth table for f 1 (a,b,c) at right The canonical sum-of-products form for f 1 is f 1 (a,b,c) = m 1 + m 2 + m 4 + m 6 = a’b’c + a’bc’ + ab’c’ + abc’ The canonical sum-of-products form for f 1 is f 1 (a,b,c) = m 1 + m 2 + m 4 + m 6 = a’b’c + a’bc’ + ab’c’ + abc’ The canonical product-of-sums form for f 1 is f 1 (a,b,c) = M 0 M 3 M 5 M 7 = (a+b+c)(a+b’+c’) (a’+b+c’)(a’+b’+c’). The canonical product-of-sums form for f 1 is f 1 (a,b,c) = M 0 M 3 M 5 M 7 = (a+b+c)(a+b’+c’) (a’+b+c’)(a’+b’+c’). Observe that: m j = M j ’ Observe that: m j = M j ’ abc f1f1f1f1 0000 0011 0101 0110 1001 1010 1101 1110

38. 1-Mar-16 PJF - 38Chapter 2-i: Combinational Logic Circuits (2.1-- 2.5) Shorthand: ∑ and ∏ f 1 (a,b,c) = ∑ m(1,2,4,6), where ∑ indicates that this is a sum-of-products form, and m(1,2,4,6) indicates that the minterms to be included are m 1, m 2, m 4, and m 6. f 1 (a,b,c) = ∑ m(1,2,4,6), where ∑ indicates that this is a sum-of-products form, and m(1,2,4,6) indicates that the minterms to be included are m 1, m 2, m 4, and m 6. f 1 (a,b,c) = ∏ M(0,3,5,7), where ∏ indicates that this is a product-of-sums form, and M(0,3,5,7) indicates that the maxterms to be included are M 0, M 3, M 5, and M 7. f 1 (a,b,c) = ∏ M(0,3,5,7), where ∏ indicates that this is a product-of-sums form, and M(0,3,5,7) indicates that the maxterms to be included are M 0, M 3, M 5, and M 7. Since m j = M j ’ for any j, ∑ m(1,2,4,6) = ∏ M(0,3,5,7) = f 1 (a,b,c) Since m j = M j ’ for any j, ∑ m(1,2,4,6) = ∏ M(0,3,5,7) = f 1 (a,b,c)

39. 1-Mar-16 PJF - 39Chapter 2-i: Combinational Logic Circuits (2.1-- 2.5) Conversion Between Canonical Forms Replace ∑ with ∏ (or vice versa) and replace those j’s that appeared in the original form with those that do not. Replace ∑ with ∏ (or vice versa) and replace those j’s that appeared in the original form with those that do not. Example: f 1 (a,b,c)= a’b’c + a’bc’ + ab’c’ + abc’ = m 1 + m 2 + m 4 + m 6 = ∑ (1,2,4,6) = ∏ (0,3,5,7) = (a+b+c)(a+b’+c’)(a’+b+c’)(a’+b’+c’) Example: f 1 (a,b,c)= a’b’c + a’bc’ + ab’c’ + abc’ = m 1 + m 2 + m 4 + m 6 = ∑ (1,2,4,6) = ∏ (0,3,5,7) = (a+b+c)(a+b’+c’)(a’+b+c’)(a’+b’+c’)

40. 1-Mar-16 PJF - 40Chapter 2-i: Combinational Logic Circuits (2.1-- 2.5) Standard Forms (NOT Unique) Standard forms are “like” canonical forms, except that not all variables need appear in the individual product (SOP) or sum (POS) terms. Standard forms are “like” canonical forms, except that not all variables need appear in the individual product (SOP) or sum (POS) terms. Example: f 1 (a,b,c) = a’b’c + bc’ + ac’ is a standard sum-of-products form Example: f 1 (a,b,c) = a’b’c + bc’ + ac’ is a standard sum-of-products form f 1 (a,b,c) = (a+b+c)(b’+c’)(a’+c’) is a standard product-of-sums form. f 1 (a,b,c) = (a+b+c)(b’+c’)(a’+c’) is a standard product-of-sums form.

41. 1-Mar-16 PJF - 41Chapter 2-i: Combinational Logic Circuits (2.1-- 2.5) Conversion of SOP from standard to canonical form Expand non-canonical terms by inserting equivalent of 1 in each missing variable x: (x + x’) = 1 Expand non-canonical terms by inserting equivalent of 1 in each missing variable x: (x + x’) = 1 Remove duplicate minterms Remove duplicate minterms f 1 (a,b,c) = a’b’c + bc’ + ac’ = a’b’c + (a+a’)bc’ + a(b+b’)c’ = a’b’c + abc’ + a’bc’ + abc’ + ab’c’ = a’b’c + abc’ + a’bc + ab’c’ f 1 (a,b,c) = a’b’c + bc’ + ac’ = a’b’c + (a+a’)bc’ + a(b+b’)c’ = a’b’c + abc’ + a’bc’ + abc’ + ab’c’ = a’b’c + abc’ + a’bc + ab’c’

42. 1-Mar-16 PJF - 42Chapter 2-i: Combinational Logic Circuits (2.1-- 2.5) Conversion of POS from standard to canonical form Expand noncanonical terms by adding 0 in terms of missing variables (e.g., xx’ = 0) and using the distributive law Expand noncanonical terms by adding 0 in terms of missing variables (e.g., xx’ = 0) and using the distributive law Remove duplicate maxterms Remove duplicate maxterms f 1 (a,b,c) = (a+b+c)(b’+c’)(a’+c’) = (a+b+c)(aa’+b’+c’)(a’+bb’+c’) = (a+b+c)(a+b’+c’)(a’+b’+c’) (a’+b+c’)(a’+b’+c’) = (a+b+c)(a+b’+c’)(a’+b’+c’)(a’+b+c’) f 1 (a,b,c) = (a+b+c)(b’+c’)(a’+c’) = (a+b+c)(aa’+b’+c’)(a’+bb’+c’) = (a+b+c)(a+b’+c’)(a’+b’+c’) (a’+b+c’)(a’+b’+c’) = (a+b+c)(a+b’+c’)(a’+b’+c’)(a’+b+c’)

43. 1-Mar-16 PJF - 43Chapter 2-i: Combinational Logic Circuits (2.1-- 2.5) Karnaugh Maps Karnaugh maps (K-maps) are graphical representations of boolean functions. Karnaugh maps (K-maps) are graphical representations of boolean functions. One map cell corresponds to a row in the truth table. One map cell corresponds to a row in the truth table. Also, one map cell corresponds to a minterm or a maxterm in the boolean expression Also, one map cell corresponds to a minterm or a maxterm in the boolean expression Multiple-cell areas of the map correspond to standard terms. Multiple-cell areas of the map correspond to standard terms.

44. 1-Mar-16 PJF - 44Chapter 2-i: Combinational Logic Circuits (2.1-- 2.5) Two-Variable Map m3m3m3m3 m2m2m2m2 1 m1m1m1m1 m0m0m0m0 0 10 x1x1x1x1 x2x2 01 2 3 NOTE: ordering of variables is IMPORTANT for f(x 1,x 2 ), x 1 is the row, x 2 is the column. Cell 0 represents x 1 ’x 2 ’; Cell 1 represents x 1 ’x 2 ; etc. If a minterm is present in the function, then a 1 is placed in the corresponding cell. m3m3m3m3 m1m1m1m11 m2m2m2m2 m0m0m0m00 10 x2x2x2x2 x1x1 02 1 3 OR

45. 1-Mar-16 PJF - 45Chapter 2-i: Combinational Logic Circuits (2.1-- 2.5) Two-Variable Map (cont.) Any two adjacent cells in the map differ by ONLY one variable, which appears complemented in one cell and uncomplemented in the other. Any two adjacent cells in the map differ by ONLY one variable, which appears complemented in one cell and uncomplemented in the other. Example: m 0 (=x 1 ’x 2 ’) is adjacent to m 1 (=x 1 ’x 2 ) and m 2 (=x 1 x 2 ’) but NOT m 3 (=x 1 x 2 ) Example: m 0 (=x 1 ’x 2 ’) is adjacent to m 1 (=x 1 ’x 2 ) and m 2 (=x 1 x 2 ’) but NOT m 3 (=x 1 x 2 )

46. 1-Mar-16 PJF - 46Chapter 2-i: Combinational Logic Circuits (2.1-- 2.5) 2-Variable Map -- Example f(x 1,x 2 ) = x 1 ’x 2 ’+ x 1 ’x 2 + x 1 x 2 ’ = m 0 + m 1 + m 2 = x 1 ’ + x 2 ’ f(x 1,x 2 ) = x 1 ’x 2 ’+ x 1 ’x 2 + x 1 x 2 ’ = m 0 + m 1 + m 2 = x 1 ’ + x 2 ’ 1s placed in K-map for specified minterms m 0, m 1, m 2 1s placed in K-map for specified minterms m 0, m 1, m 2 Grouping (ORing) of 1s allows simplification Grouping (ORing) of 1s allows simplification What (simpler) function is represented by each dashed rectangle? What (simpler) function is represented by each dashed rectangle? x 1 ’ = m 0 + m 1 x 1 ’ = m 0 + m 1 x 2 ’ = m 0 + m 2 x 2 ’ = m 0 + m 2 Note m 0 covered twice Note m 0 covered twice x1x1x1x101 011 110 x2x2 01 23

47. 1-Mar-16 PJF - 47Chapter 2-i: Combinational Logic Circuits (2.1-- 2.5) Minimization as SOP using K-map Enter 1s in the K-map for each product term in the function Enter 1s in the K-map for each product term in the function Group adjacent K-map cells containing 1s to obtain a product with fewer variables. Groups must be in power of 2 (2, 4, 8, …) Group adjacent K-map cells containing 1s to obtain a product with fewer variables. Groups must be in power of 2 (2, 4, 8, …) Handle “boundary wrap” for K-maps of 3 or more variables. Handle “boundary wrap” for K-maps of 3 or more variables. Realize that answer may not be unique Realize that answer may not be unique

48. 1-Mar-16 PJF - 48Chapter 2-i: Combinational Logic Circuits (2.1-- 2.5) Three-Variable Map m6m6m6m6 m7m7m7m7 m5m5m5m5 m4m4m4m41 m2m2m2m2 m3m3m3m3 m1m1m1m1 m0m0m0m0010110100yz x 0132 4576 -Note: variable ordering is (x,y,z); yz specifies column, x specifies row. -Each cell is adjacent to three other cells (left or right or top or bottom or edge wrap)

49. 1-Mar-16 PJF - 49Chapter 2-i: Combinational Logic Circuits (2.1-- 2.5) Three-Variable Map (cont.) The types of structures that are either minterms or are generated by repeated application of the minimization theorem on a three variable map are shown at right. Groups of 1, 2, 4, 8 are possible. minterm group of 2 terms group of 4 terms

50. 1-Mar-16 PJF - 50Chapter 2-i: Combinational Logic Circuits (2.1-- 2.5) Simplification Enter minterms of the Boolean function into the map, then group terms Enter minterms of the Boolean function into the map, then group terms Example: f(a,b,c) = a’c + abc + bc’ Example: f(a,b,c) = a’c + abc + bc’ Result: f(a,b,c) = a’c + b Result: f(a,b,c) = a’c + b 111 11 a bc11111 0 1 0 1

51. 1-Mar-16 PJF - 51Chapter 2-i: Combinational Logic Circuits (2.1-- 2.5) More Examples f 1 (x, y, z) = ∑ m(2,3,5,7) f 1 (x, y, z) = ∑ m(2,3,5,7) f 2 (x, y, z) = ∑ m (0,1,2,3,6) f 2 (x, y, z) = ∑ m (0,1,2,3,6) f 1 (x, y, z) = x’y + xz f 1 (x, y, z) = x’y + xz f 2 (x, y, z) = x’+yz’ f 2 (x, y, z) = x’+yz’ yz yzX00011110 011 111 11111

52. 1-Mar-16 PJF - 52Chapter 2-i: Combinational Logic Circuits (2.1-- 2.5) Four-Variable Maps Top cells are adjacent to bottom cells. Left- edge cells are adjacent to right-edge cells. Top cells are adjacent to bottom cells. Left- edge cells are adjacent to right-edge cells. Note variable ordering (WXYZ). Note variable ordering (WXYZ). m 10 m 11 m9m9m9m9 m8m8m8m8 10 m 14 m 15 m 13 m 12 11 m6m6m6m6 m7m7m7m7 m5m5m5m5 m4m4m4m4 01 m2m2m2m2 m3m3m3m3 m1m1m1m1 m0m0m0m0 00 10 10 11 11 01 01 00 00 WX YZ

53. 1-Mar-16 PJF - 53Chapter 2-i: Combinational Logic Circuits (2.1-- 2.5) Four-variable Map Simplification One square represents a minterm of 4 literals. One square represents a minterm of 4 literals. A rectangle of 2 adjacent squares represents a product term of 3 literals. A rectangle of 2 adjacent squares represents a product term of 3 literals. A rectangle of 4 squares represents a product term of 2 literals. A rectangle of 4 squares represents a product term of 2 literals. A rectangle of 8 squares represents a product term of 1 literal. A rectangle of 8 squares represents a product term of 1 literal. A rectangle of 16 squares produces a function that is equal to logic 1. A rectangle of 16 squares produces a function that is equal to logic 1.

54. 1-Mar-16 PJF - 54Chapter 2-i: Combinational Logic Circuits (2.1-- 2.5) Example Simplify the following Boolean function (A,B,C,D) = ∑m(0,1,2,4,5,7,8,9,10,12,13). Simplify the following Boolean function (A,B,C,D) = ∑m(0,1,2,4,5,7,8,9,10,12,13). First put the function g( ) into the map, and then group as many 1s as possible. First put the function g( ) into the map, and then group as many 1s as possible. cd ab 1 11 11 1 11 1 11 g(A,B,C,D) = c’+b’d’+a’bd 111 11 111 111

55. 1-Mar-16 PJF - 55Chapter 2-i: Combinational Logic Circuits (2.1-- 2.5) 5-Variable K-Map 101198 13141512 5674 1230 BC DE 26 26 27 27 25 25 24 24 30 30 31 31 29 29 28 28 22 22 23 23 21 21 20 20 18 18 19 19 17 17 16 16 BC DE A=0 A=1 A’BCDE’ ABCDE’

56. 1-Mar-16 PJF - 56Chapter 2-i: Combinational Logic Circuits (2.1-- 2.5) Implicants and Prime Implicants (PIs) An Implicant (P) of a function F is a product term which implies F, i.e., F(P) = 1. An Implicant (P) of a function F is a product term which implies F, i.e., F(P) = 1. An implicant (PI) of F is called a Prime Implicant of F if any product term obtained by deleting a literal of PI is NOT an implicant of F An implicant (PI) of F is called a Prime Implicant of F if any product term obtained by deleting a literal of PI is NOT an implicant of F Thus, a prime implicant is not contained in any “larger” implicant. Thus, a prime implicant is not contained in any “larger” implicant.

57. 1-Mar-16 PJF - 57Chapter 2-i: Combinational Logic Circuits (2.1-- 2.5) Example Consider function f(a,b,c,d) whose K-map is shown at right. Consider function f(a,b,c,d) whose K-map is shown at right. a’b’ is not a prime implicant because it is contained in b’. a’b’ is not a prime implicant because it is contained in b’. acd is not a prime implicant because it is contained in ad. acd is not a prime implicant because it is contained in ad. b’, ad, and a’cd’ are prime implicants. b’, ad, and a’cd’ are prime implicants. 111 111 111 11 b’ cd ab ad a’cd’ a’b’ acd

58. 1-Mar-16 PJF - 58Chapter 2-i: Combinational Logic Circuits (2.1-- 2.5) Essential Prime Implicants (EPIs) If a minterm of a function F is included in ONLY one prime implicant p, then p is an essential prime implicant of F. If a minterm of a function F is included in ONLY one prime implicant p, then p is an essential prime implicant of F. An essential prime implicant MUST appear in all possible SOP expressions of a function An essential prime implicant MUST appear in all possible SOP expressions of a function To find essential prime implicants: To find essential prime implicants: Generate all prime implicants of a function Generate all prime implicants of a function Select those prime implicants that contain at least one 1 that is not covered by any other prime implicant. Select those prime implicants that contain at least one 1 that is not covered by any other prime implicant. For the previous example, the PIs are b’, ad, and a’cd’; all of these are essential. For the previous example, the PIs are b’, ad, and a’cd’; all of these are essential. 111 111 111 11 b’ ad a’cd’

59. 1-Mar-16 PJF - 59Chapter 2-i: Combinational Logic Circuits (2.1-- 2.5) The Other Example Consider f 2 (a,b,c,d), whose K-map is shown below. Consider f 2 (a,b,c,d), whose K-map is shown below. The only essential PI is b’d. The only essential PI is b’d. 1 111 11 111 cd ab

60. 1-Mar-16 PJF - 60Chapter 2-i: Combinational Logic Circuits (2.1-- 2.5) Systematic Procedure for Simplifying Boolean Functions 1. Generate all PIs of the function. 2. Include all essential PIs. 3. For remaining minterms not included in the essential PIs, select a set of other PIs to cover them, with minimal overlap in the set. 4. The resulting simplified function is the logical OR of the product terms selected above.

61. 1-Mar-16 PJF - 61Chapter 2-i: Combinational Logic Circuits (2.1-- 2.5) Example f(a,b,c,d) = ∑m(0,1,2,3,4,5,7,14,15). f(a,b,c,d) = ∑m(0,1,2,3,4,5,7,14,15). Five grouped terms, not all needed. Five grouped terms, not all needed. 3 shaded cells covered by only one term 3 shaded cells covered by only one term 3 EPIs, since each shaded cell is covered by a different term. 3 EPIs, since each shaded cell is covered by a different term. F(a,b,c,d) = a’b’ + a’c’ + a’d + abc F(a,b,c,d) = a’b’ + a’c’ + a’d + abc 11 111 1111 ab cd

62. 1-Mar-16 PJF - 62Chapter 2-i: Combinational Logic Circuits (2.1-- 2.5) Product of Sums Simplification Product of Sums Simplification Use sum-of-products simplification on the zeros of the function in the K-map to get F’. Use sum-of-products simplification on the zeros of the function in the K-map to get F’. Find the complement of F’, i.e. (F’)’ = F Find the complement of F’, i.e. (F’)’ = F Recall that the complement of a boolean function can be obtained by (1) taking the dual and (2) complementing each literal. Recall that the complement of a boolean function can be obtained by (1) taking the dual and (2) complementing each literal. OR, using DeMorgan’s Theorem. OR, using DeMorgan’s Theorem.

63. 1-Mar-16 PJF - 63Chapter 2-i: Combinational Logic Circuits (2.1-- 2.5) POS Example 0000 1100 0111 1111 ab cd F’(a,b,c,d) = ab’ + ac’ + a’bcd’ Find dual of F’, dual(F’) = (a+b’)(a+c’)(a’+b+c+d’) Complement of literals in dual(F’) to get F F = (a’+b)(a’+c)(a+b’+c’+d)

64. 1-Mar-16 PJF - 64Chapter 2-i: Combinational Logic Circuits (2.1-- 2.5) Don't Care Conditions There may be a combination of input values which There may be a combination of input values which will never occur will never occur if they do occur, the output is of no concern. if they do occur, the output is of no concern. The function value for such combinations is called a don't care. The function value for such combinations is called a don't care. They are denoted with x or –. Each x may be arbitrarily assigned the value 0 or 1 in an implementation. They are denoted with x or –. Each x may be arbitrarily assigned the value 0 or 1 in an implementation. Don’t cares can be used to further simplify a function Don’t cares can be used to further simplify a function

65. 1-Mar-16 PJF - 65Chapter 2-i: Combinational Logic Circuits (2.1-- 2.5) Minimization using Don’t Cares Treat don't cares as if they are 1s to generate PIs. Treat don't cares as if they are 1s to generate PIs. Delete PI's that cover only don't care minterms. Delete PI's that cover only don't care minterms. Treat the covering of remaining don't care minterms as optional in the selection process (i.e. they may be, but need not be, covered). Treat the covering of remaining don't care minterms as optional in the selection process (i.e. they may be, but need not be, covered).

66. 1-Mar-16 PJF - 66Chapter 2-i: Combinational Logic Circuits (2.1-- 2.5) Example Simplify the function f(a,b,c,d) whose K-map is shown at the right. Simplify the function f(a,b,c,d) whose K-map is shown at the right. f = a’c’d+ab’+cd’+a’bc’ f = a’c’d+ab’+cd’+a’bc’or f = a’c’d+ab’+cd’+a’bd’ f = a’c’d+ab’+cd’+a’bd’ The middle two terms are EPIs, while the first and last terms are selected to cover the minterms m 1, m 4, and m 5. The middle two terms are EPIs, while the first and last terms are selected to cover the minterms m 1, m 4, and m 5. (There’s a third solution!) (There’s a third solution!) xx11 xx00 10111010 xx11 xx00 10111010 0101 1101 00xx 11xx ab cd 00 01 11 10 00 01 11 10

67. 1-Mar-16 PJF - 67Chapter 2-i: Combinational Logic Circuits (2.1-- 2.5) The Other Example Simplify the function g(a,b,c,d) whose K-map is shown at right. Simplify the function g(a,b,c,d) whose K-map is shown at right. g = a’c’+ ab or g = a’c’+ ab or g = a’c’+bd’ g = a’c’+bd’ x100 1x0x 1xx1 0xx0 x1001x0x 1xx1 0xx0 x1001x0x 1xx1 0xx0 ab cd

68. 1-Mar-16 PJF - 68Chapter 2-i: Combinational Logic Circuits (2.1-- 2.5) Algorithmic minimization What do we do for functions with more than 4-5 variables? What do we do for functions with more than 4-5 variables? You can “code up” a minimizer (Computer-Aided Design, CAD) You can “code up” a minimizer (Computer-Aided Design, CAD) Quine-McCluskey algorithm Quine-McCluskey algorithm Iterated consensus Iterated consensus We won’t discuss these techniques here We won’t discuss these techniques here

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