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EDR GEM - LNF 5/2/05Walter Bonivento - INFN Cagliari1 FRONT-END and HV 1)System architecture: brief summary 2)Status of chips production 3)Front-end board.

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Presentation on theme: "EDR GEM - LNF 5/2/05Walter Bonivento - INFN Cagliari1 FRONT-END and HV 1)System architecture: brief summary 2)Status of chips production 3)Front-end board."— Presentation transcript:

1 EDR GEM - LNF 5/2/05Walter Bonivento - INFN Cagliari1 FRONT-END and HV 1)System architecture: brief summary 2)Status of chips production 3)Front-end board for the wire-chambers: status 4)First prototype of front-end board for GEMs 5)Tests performed 6)Front-end chip for GEMs 7)Radiation hardness 8)Organisation and responsibilities 9)Grounding issues 10)HV

2 EDR GEM - LNF 5/2/05Walter Bonivento - INFN Cagliari2 The LHCb muon electronics project Common project with wire chambers: 1)same far-end structure 2)same front-end board conception: 2 CARIOCA chips + 1 DIALOG chip 3)same bids and producing companies 4)same people BUT 1)CARIOCA  CARIOCA GEM 2)front end board (CARDIAC) of different size and layout 3)SPB integrated on the CARDIAC 4)different cables and connectors space requirememnts

3 EDR GEM - LNF 5/2/05Walter Bonivento - INFN Cagliari3 System architecture Triple_GEM det a F/E board 8 PCH ASD 8 LCH DIALOG ON DETECTOR ELECTRONICS I 2 C MASTER LOW VOLTAGE CONTROLS CALIBRATION PULSES SERVICE board (on crates) SYNCHRONIZATION TIME (PHASE) MEASUREMENT DATA FORMATTING DATA TO MUON TRIGGER OFF DETECTOR ELECTRONICS 10m cabling (LVDS) DATA TO DAQ RECONSTRUCTION Counting Room Triple_GEM det b

4 EDR GEM - LNF 5/2/05Walter Bonivento - INFN Cagliari4 CARIOCA Discriminator threshold can be individually set to compensate for offset from process variation internal test structure to inject signal from DIALOG to CARIOCA input; minimum injected charge 50fC  only checks if channel ON/OFF At Cdet=15-30pF, t r =8ns, Zin=50Ω, ENC=0.5-0.6fC linear up to 200fC shaper, 2pole-zero ion tail cancellation active BLR All differential circuitry, unipolar shaping  DC coupled (CERN + CBPF Rio) IBM 0.25 μm radiation tolerant technology 8 analog input channels 8 LVDS output channels gain about 12mV/fc @ Cdet=15-30pF VERY SIMILAR CHARACTERISTICS TO ASDQ

5 EDR GEM - LNF 5/2/05Walter Bonivento - INFN Cagliari5 DIALOG generates logical channels by OR-ing of two face-to-face physical channels provides a masking facility to access single channels threshold DAC and line drivers for the CARIOCA chip integrates 16 8-bit DACs with output buffer to set the CARIOCA discriminator threshold with about 0.17fC granularity Programmable delays  31 steps of 1.6ns  50ns max Digital shaping  output signal width 8 steps of 3ns  25ns max Front-end rate and noise monitor 16 24-bits rate counters all functionalities can be controlled via I 2 C interface Triple-voted and auto-corrected register for better SEU immunity INFN -CA IBM 0.25 μm radiation tolerant technology 16 LVDS input channels 8 LVDS output channels

6 EDR GEM - LNF 5/2/05Walter Bonivento - INFN Cagliari6 Chip NRE run submission RETICULE: 4 CARIOCA, 2 DIALOG, 1 SYNC 1 CARIOCAGEM. Reticule size 15.3 x 8.1 mm 2 Reticules/wafer ~ 205  Chips per wafer: 820 CARIOCA, 410 DIALOG, 205 SYNC, 205 CARIOCAGEM Expected  CARIOCACARIOCAGEMDIALOGSYNCComments NRE49201230246012306 wafers Production39360984019680984048 wafers Needed24000800120006000Assuming 80% yield and 20% spares Submitted in September, Wafers Received in November, Packaged circuits to be delivered next week

7 EDR GEM - LNF 5/2/05Walter Bonivento - INFN Cagliari7 Wire chamber front-end boards CARDIAC 63mm 50mm DCC final DIALOG final CARIOCA CARDIAC 2.0 on wire-chamber More extensively tested 6 layers: signal, GND, LV, signal,GND,signal power consumption 0.5A  1.25W

8 EDR GEM - LNF 5/2/05Walter Bonivento - INFN Cagliari8 CARDIAC About 20 boards of CARDIAC 2.0 produced and tested Good experience now with the PVSS/CANBUS system (Rome I) to communicate with and program the DIALOG chip via I2C bus Many measurements in the Lab (Cagliari and Potenza-Rome1): performance almost OK Experience with CARDIAC 2.0

9 EDR GEM - LNF 5/2/05Walter Bonivento - INFN Cagliari9 Experience with CARDIAC 2.0 Study of the efficiency and time properties to test: - the front-end electronics reliability; - high rate on the chamber The tests were completely satisfactory Test at GIF (CERN): fully equipped M3R2 wire-chamber 12 CARDIAC boards: The same number of I2C lines as for triple-GEM chambers!!! 2 I2C long lines chains and 1 SB controlled via CANBUS by a PVSS program

10 EDR GEM - LNF 5/2/05Walter Bonivento - INFN Cagliari10 The front end board for GEMs: CARDIAC GEM CARDIACGEM 1.0 : a very first prototype  3 boards assembled Tight space requirements  45x70mm length and 14mm thichkness Two boards in one: FEB+SPB Spark protection on the bottom; the 3 chips on the top Spark protection circuit: only 500V  simplified  two resistors+2 double diodes -> to be tested (the one of WPC well tested) New type of connectors and cables  pitch reduced by half need a special cable 0.635mm pitch top bottom 70mm 45mm I2C LV LVDS

11 EDR GEM - LNF 5/2/05Walter Bonivento - INFN Cagliari11 How the board is plugged in Minimum space available on the top for cables 5-6mm

12 EDR GEM - LNF 5/2/05Walter Bonivento - INFN Cagliari12 Lab tests of CARDIAC (-GEM) Standard lab tests (also at the Company assembling the boards) gain curve S-curve Cdet=15pF Problem: due to process variations  spread in gain curve parameters: a)SLOPE b) INTERCEPT If one threshold value for all channels is set, then about 1fC rms effective threshold spread is obtained ENC~05-06fC; not depending on channel position too much for GEMs (we want to trigger at ~2-2.5fC) remember: WPC trigger at 6-7fC  much less of a problem…

13 EDR GEM - LNF 5/2/05Walter Bonivento - INFN Cagliari13 Lab tests of CARDIAC (-GEM) (II) STRATEGY to reduce the threshold spread: 1)measure noise counts vs. TH curve 2)correct for the intercept spread in two ways: a) equalising minimum thresholds(>0!! in this chip) b) equalising noise count values effective threshold spread is reduced to about 0.5fC(a) or 0.7fC(b) rms This can be done in LHCb and continously monitored! y~erfc(x)

14 EDR GEM - LNF 5/2/05Walter Bonivento - INFN Cagliari14 Lab tests of CARDIAC (-GEM) (III) A further improvement of the threshold spread (reducing it to ~0fC) can be obtained in the lab: 1)measuring directly the gain at the assembling company and keeping a database (foreseen in the contract) ΔG/G(%)=0.5x ΔT( 0 C) =20mV of power supply the same cannot be done for the intercepts since e.g. ΔG/G(%)= 1mV of power supply!!!  20mV in supply voltage moves the intercept by 20% !!!!  the slope is much less sensistive than the intercept to supply voltage variations  we are lucky that the intercept spread can be compensated for with the other method… 2) injecting a calibration pulse on G3down (to be tested)

15 EDR GEM - LNF 5/2/05Walter Bonivento - INFN Cagliari15 Lab Test with GEM chamber (HV off) Count rates on 3 chambers with ~3fC threshold below a kHz (most channels << 1kHz) Very preliminary test NB: cables to be replaced, no FC, simplified GND…

16 EDR GEM - LNF 5/2/05Walter Bonivento - INFN Cagliari16 Why CARIOCA GEM and how Two main reasons: 1)minimum threhsold: in beam tests with ASDQ it was set to 2fC; with CARIOCA10 the minimum is 2.5-3.3fC 2) due to ion tail cancellation in the CARIOCA shaping circuit  afterpulses  10-15 V loss in plateau with CARIOCA

17 EDR GEM - LNF 5/2/05Walter Bonivento - INFN Cagliari17 The triple-GEM detector signal Signal formation: same as pulse mode ionisation chamber Primary ionisation and drift 1 ionisation cluster 5 ionisation clusters Example: 5 primary cluster signal

18 EDR GEM - LNF 5/2/05Walter Bonivento - INFN Cagliari18 signal shapes CARIOCA10 δ SPICE CARIOCAGEM δ CARIOCA10 (1cl) CARIOCAGEM (1cl) CARIOCAGEM (m.i.p. signal) CARIOCA10 (m.i.p. signal)

19 EDR GEM - LNF 5/2/05Walter Bonivento - INFN Cagliari19 Afterpulses with ion tail cancellation two reasons: 1) undershoot 2) inside the event: different gain of clusters blow up irreducible fraction of afterpulses  10%-15% simulation

20 EDR GEM - LNF 5/2/05Walter Bonivento - INFN Cagliari20 FEB Production test strategy Tests of the produced chips will be performed by the same company performing sawing and packaging Five company already contacted (Microtest, Microtec, DELTA, Edgetek, HCM). Order procedure is under preparation. This is sure in the case of DIALOG and SYNC. Concerning CARIOCA still some discussion (interest of CBPF – Rio + Brazilian company). Decision to be taken in the next two weeks. FEB production test  company with a tool developed by INFN RomaI @Potenza

21 EDR GEM - LNF 5/2/05Walter Bonivento - INFN Cagliari21 Next steps CARDIAC-GEM 1.1 under design: some changes (cross- talk improvements)  it will have CARIOCAGEM same bids and orders as CARDIAC Order for final PCB production placed  Gerber files not yet sent Tender for board assembling + testing (with equipment provided by Rome I+PZ group) started  order placed in ~1.5months some pre-production expected first(50 boards) and after measurements the rest of the boards

22 EDR GEM - LNF 5/2/05Walter Bonivento - INFN Cagliari22 Radiation hardness Total dose in M1/R1: 500 kRad in 10y Both chips 0.25μn CMOS rad tolerant design no digital circuitry 2 chips of a previous version tested for total dose up to 10MRad  sensitivity decrease < 3.5%  sensitivity spread unchanged  threshold moved by 10-20mV (1fC) tested for total dose up to 1MRad with 60 Co source tested for SEE @ PSI 250 MeV p; flux=6x10 8 cm -2 s -1 without activating self correction #SEE<1 in 10 days for total fluence of 10 13 p/cm -2 (10 LHCb years in M1/R1) CARIOCA DIALOG

23 EDR GEM - LNF 5/2/05Walter Bonivento - INFN Cagliari23 Grounding The proposed grounding scheme follows the one of WPC and requires : 1. FC as detector signal ground reference 2. Floating low voltage power supply 3. Chamber connected only to the safety ground 4. I2C ground broken by 100KΩ resistor on FEB 5. LVDS GND not connected; all GNDs put together at FE racks 6.LVDS cable shields connected to GND at the rack side

24 EDR GEM - LNF 5/2/05Walter Bonivento - INFN Cagliari24 LV Power consumption/board=0.5A Supply voltage =2.5V #boards =24/chamber  #boards/rad tol regulator=3;  #rad tol regulators/chamber=8; some prototype boards for WPC exist engineering for GEM (tight clearance!) under design So far LV distribution was performed with LV boards placed on the chamber with non rad tolerant regulators  in LHCb we have to go to rad tol regulator(STM-CERN design)  same as for LHCb wire-chambers boards were fed with LV from a min-bus (not in series!)

25 EDR GEM - LNF 5/2/05Walter Bonivento - INFN Cagliari25 HV: a resistive divider chain So far: 7 HV channels/gap: the easiest and the most expensive but very dangerous in case of a trip at least the GEMs should be together divider ΔVg em2 1)6kV/1mA 2)4kV/2mA 3)1.3kV/10mA Requirements: 1.stay in plateau with 10 μA in the detector in LHCb 2.limit power consumption 3.protect GEMs in case of sparks 4.monitor current in the detector  a candidate solution with 3 dividers and 3 commercial power supplies (CAEN) monitor of 3-GEM current ! total Power consumption 15 W at plateau end Prototype of Al 2 O 3 with dissipating bottom layer and trimmed serigraphed resistors under design g2 g1  50   2.2 nF 5  5   10 nF 5   nF     g3   /sector

26 EDR GEM - LNF 5/2/05Walter Bonivento - INFN Cagliari26 Resistive divider chain: SPICE simulation plateau 1280V to 1350V 8V SPICE simulation based on measurements from our group: see TNS 49(2002)1638 voltage drop Δ Vsum Δ V 1,2,3 Effect of a spark: HV recovery time 1)main sector 2)neighbour sector SPICE simulation based on measurements from our group: see TNS 49(2002)1638 5ms spark Δ V 1,2,3

27 EDR GEM - LNF 5/2/05Walter Bonivento - INFN Cagliari27 Test of the divider chain in the lab LHCb divider chain designed to have minimal drop To test our simulation a divider was built with 10k larger value resistors (standard HV – CERN store) than what we need in LHCb  much larger drop Two radioactive sources Sr and Ru Four readings: 1)I(pad)  1 to 2.3μA (0.5 LHCb!!) 2)I (power supply divider)  180μA 3)I(power supply cathode)  0.3-0.7μA 4)ΔV on the 3 rd GEM where the maximum drop is expected  3-5V agreement with simulation within 50% (in the LHCb version we expect 5%  OK!!)  more tests with x-rays to come Triple-GEM chamber 10x10cm 2 one divider cathode independently fed with HV

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