1. New RPC Front-End Electronics for HADES
A. Gil a, D. Belver b, P. Cabanelas b, J. Díaz a, J.A. Garzón b, D. González-Díaz b, W. Koenig c, J.S. Lange c, J. Marín d, N. Montes b, P. Skott c, M. Traxler c
a IFIC (Centro Mixto UV-CSIC) Valencia, 46071, Spain.
b LabCAF, Dpto. de Física de Partículas, Universidade de Santiago de Compostela, Santiago de Compostela, 15782, Spain.
c GSI, Darmstadt,64291, Germany.
d CIEMAT, Avd. Complutense 22, Madrid, 28040, Spain.
In this presentation I will show the new front End Electronics for the Hades Experiment
Actually there are 3 groups in Spain and 1 germany at GSI involved in the project.
18 segundos
12th Workshop on Electronics for LHC and future Experiments
25-29 September 2006
Valencia (Spain)

2. OUTLINE HADES EXPERIMENT RESISTIVE PLATE CHAMBER (RPC) WALL RPC CELLS
RPC SIGNALS
ELECTRONIC CHAIN
FRONT-END ELECTRONICS
RESULTS
IMPROVEMENTS
SUMMARY

3. HADES EXPERIMENT
HADES is located at the SIS accelerator of GSI, Darmstadt (Germany)
GSI
Hades is placed at the SIS accelerator of GSI, Darmstadt (Germany).
8 segundos
FAIR
HADES

4. High Acceptance DiElecton Spectrometer
HADES EXPERIMENT
High Acceptance DiElecton Spectrometer
Detection of electron-positron pairs produced in relativistic hadron-nucleus and nucleus-nucleus collisions with the goal of studying vector meson properties in nuclear matter, both normal and hot and compressed.
Consists of several subdetectors providing tracking, triggering, particle identification and momentum reconstruction capabilities
HADES is a High accepatance di electon spectrometer, (that detects electron pairs) for the detecion of electron-positron pairs produced in relativistic hadron-nucleus and nucleus –nucleus collisions with the goal of studying vector meson properties in nuclear matter, both normal and hot compressed.
Consists of several subdetectos providing tracking, triggering, particle identification and momentum reconstruction capabilities.
17 segundos
TOT 63 seg
RPC detector

5. (cross section of HADES)
HADES EXPERIMENT
Objective of the project:
Upgrade of HADES replacing the low angle TOFino detector for the an RPC wall
TOF: Time of Flight detector (100ps time resolution)
TOFino: Low angle Time of Flight detector (350ps time resolution)
RPC wall
The picture shows the cross section of HADES, which has several detectors:
RICH surrounds the target for detection of electrons and positrons
Multi-Wire Drift chambers: track particles
TOF: time of flight measurement and is made of plastic scintillator rods.
Shower: particle multiplicity to trigger on collision centrality.
The lower angle region of the TOF detector is called Tofino. This region will be replaced for the RPC wall.
is a diamond detector. Is
first detector wich
Surrounds the target.
Crucial for lepton identification. Blind to hadron.
Multi-wire Drift Chambers :
Are used for track reconstruction before and after the magnetic field with space resolutions below 140um.
TOF wall: is made of Plastic scintillator rods and provides Multiplicity condition. High resolution timing for sepatarion of leptons from fast pions. Time resol ps. Space resol cm. 45º<θlab<85º
Shower detector: To increase hadron rejection.
TOFino: angles below 45º. Scintillator rods. Time resol 350ps. Temporary.
1minuto 5 segundos
TOFino
(cross section of HADES)

6. RPC wall
The RPC wall is distributed in 6 sectors, covering an active area of 7 squared-meters.
(View from inside)
The RPC wall is distributed in sectors. The image shows 2 of them. There will be 6 sectors in total, covering an active area of 7 squared meters.
15 segundos

7. RPC wall 80 times larger granularity Time resolutions of 70 ps
RPC wall contains 1024 double-sided readout detectors (2048 channels)
80 times larger granularity
Time resolutions of 70 ps
Rates up to 700 Hz/cm2
collisions from C-C to Au-Au
The image shows the way the RPC cells will be set up on each sector. It contains more than 1000 detector cells
The RPC wall will allow 80 times larger granularity *****The time resolutions obtained are 70ps (5 times larger than the old detector)
Counting rates of about 700hz/cm2 will allow collisions from C-C to Au-Au
There are two layers of cells to increase the acceptance of the wall.
32 segundos
Total: 2min y 54 segundos
Double layer  acceptance close to 100%

8. RPC cells RPC Gas Box & cells(LIP-Coimbra,P. Fonte et al.)
CHEAP MATERIALS:
Aluminium
Glass
SHIELDED CELLS:
Crosstalk < 1%
GAS MIXTURE:
Freon (85%)
SF6 (15%)
Isobutane (5%)
This is the cross section structure of the cells. Formed with Al and Window glass (which are very cheap materials).
Every cell is shielded to reduce the crosstalk. Levels measured are below 1%.
It is a gaseus detector, containing Freon, SF6 and Isobutane, and works in avalanche mode.
The design of the cells and the gas-box is performed in Coimbra by Paulo Fonte and his group.
37 segundos
3:34

9. RPC signal Rise time ~500ps 5ns width Amplitudes up to 200mV
Oscillations due to impedance mismatch between the detector (20Ω) and the electronics (50Ω)
100mV
100ns
The yellow trace shows the typical shape of an RPC signal. RPC signals have an amplitud from 1mv to 50mV and about 500ps rise time.
The output of the FrontEnd electronics provides a pulse signal, where The leading edge gives information of the arrival time of the RPC signal and the width of the pulse provides information about the charge.
We use two comparators to obtain this output signal. A single edge comparator acts over the amplified RPC to produce the rising edge when the RPC signal appears,
a second comparator produces the trailing edge for width measurement. This is done with the time over threshold method, where the RPC signal is shaped through an integrator and a comparator with negative threshold that detects the zero crossing point of the integrated signal.
This is performed by a board called Daughterboard

10. FEE design considerations
A large bandwidth to deal with short rise times of RPC pulses (about 500ps rise time and 5ns width).
Low electronic jitter and noise for good time resolutions
Charge measurement for correction
Output signal for the trigger logic of HADES.
Rate < 1kHz/cm2 RPC area
x100cm2 =100kHz
X31 channels = 3.1 MHz firing
Size restrictions  two boards DB and MB
Built with commercially available components
Moderate power consumption to reduce heat.
Detector active area
The Front End electronics requires a large bandwith due to the short rise times of the RPC pulses,
It has low noise levels, to keep the cross talk levels provided by the RPC shielding
Provides time resolutions below 100ps that will be corrected with the charge information to reduce this value to 70 ps
LVDS output signals
Has an trigger output signal
Is built with commercially available components, there are size restrictions an the consume must be moderate to avoid heating problems.
Front End set up on the RPC sector

11. DAUGHTERBOARD
Generates a time-window signal which contains information about the:
Arrival time of the RPC signal (for TOF measurement)
Charge of the RPC signal
6 Layer board
4 channels/board
Micro Lemo inputs
Hi-freq Samtec connector 4 2
4.5cm
5cm

12. DAUGHTERBOARD Amplifier stage → GALI-S66 Discriminator stage:
- Dual MAX 9601 comparator with histeresis and latch enable (2 comparators/channel).
PECL-LVDS TI SN65LVDT100 converter.
BFT92 transistor for multiplicity trigger.
4 ch. out C
Integrator
Amplifier
PECL-
LVDS
ToF-Threshold
ToT-Threshold In
OPA690 Wideband
Op. Amplifier
GALI-S66 Monolithic
(20dB, 2GHz)
MAX9601-2ch 500ps Propagation Delay
SN65LVDT100
Latch enable
MAX9601-2ch R
2k2
Trigger
Out.
Σ4ch.
SAMTEC
16 diff. pins
BFT92 Wideband PNP Transistor
Comparator
The figure shows the block diagram of the daughterboard.
First the RPC signal is amplified with a GHz bandwith amplifier.
Then the circuit is divided in two branches:
In one hand there is a single edge comparator for the detection of the arrival time of the RPC signal.
On the other side there is a shaper, which is an integrator and after this other single edge comparator for the detection of the zero crossing of the integrated signal, thus determining the with of the output signal, which is proportional to the charge
The charge comparator acts over the latch enable of the time comparator to keep the output latched until the desactivation of the second comparator

13. RC integrator 2ns (to avoid tail)
RPC signal
ToF xG
RPC signal ƒ
ToT
Voltage (50mV/div)
Integrated signal
RC integrator 2ns (to avoid tail)
RPC arrival time
ToT
The yellow trace shows the typical shape of an RPC signal. RPC signals have an amplitud from 1mv to 50mV and about 500ps rise time.
The output of the FrontEnd electronics provides a pulse signal, where The leading edge gives information of the arrival time of the RPC signal and the width of the pulse provides information about the charge.
We use two comparators to obtain this output signal. A single edge comparator acts over the amplified RPC to produce the rising edge when the RPC signal appears,
a second comparator produces the trailing edge for width measurement. This is done with the time over threshold method, where the RPC signal is shaped through an integrator and a comparator with negative threshold that detects the zero crossing point of the integrated signal.
This is performed by a board called Daughterboard
Amplified RPC signal
Output signal
width~charge
Time (20ns/div)

14. MOTHERBOARD Main tasks: Supply stable voltage to the Daughterboard
6cm
40cm
Main tasks:
Supply stable voltage to the Daughterboard
+5V,-5V,+3.3V
Conentrates the time-window signals from 8 Daughterboard to 1 connector (then twisted pair cable to the TDC board).
Combines the 32 trigger signals coming out from the Daughterboard to provide only 1 multiplicity signal.
Allocates DACs for the threshold voltages of the comparators on the Daugherboard
Minor tasks:
Test signals multiplexing, LVDS repeaters,interface for DACs
programming, etc

15. MOTHERBOARD 1) Supply stable voltage to the Daughterboard
Ripple filtering
DC-DC converter
Motherboard
+5V
-5V
+3.3V
Different decades C
Ferrite bead
Uses the plugged vias technique to:
reduce ESR and ESL layout effects in filter capacitors and PCB dimensions

16. MOTHERBOARD
2)Conentrates the time-window signals from 8 Daughterboard to 1 connector (then twisted pair cable to the TDC board).
Interface: Low Voltage Differential Signaling (LVDS)
Also used for:
DACs programming
Test signals delivery
Advantages:
Low power consumption
High noise inmunity
Diferential impedance matching lines and termination resistors (100Ω) to reduce signal reflections/distorsions

17. MOTHERBOARD
3) Combines the 32 trigger signals coming out from the Daughterboard to provide only 1 multiplicity signal.
Low level trigger:
Two-stage circuit
Summing OPAMs
OPA690
High slew rate
High output swing
-100mV contribution
per channel

18. MOTHERBOARD
4) Allocates DACs for the threshold voltages of the comparators on the Daugherboard
TDC board
DO CS CLK
DAC1
DAC2
DAC8
Motherboard
DACs Thresholds
8 DACs/Motherboard
8 Channels/DAC
LTC2620
12 bits resolution
Low noise
Low power consumption
Daisy-chained
SPI programming

19. ELECTRONIC CHAIN Daughterboard 4 channels
Motherboard
Daughterboard 4 channels
Motherboard8 Daughterboards
Time Readout Board (TRB)
4 Motherboards
DC-DC converter 2 MB.
RPC
TRB
Every Daughterboard has 4 channels, which encodes signals from 2 detectors.
Every encoded signal is transmitted to the data adquisition system through the Motherboard, which holds 8 DBs.
DC-DC converter

20. TRB Time Readout Board: Custom TDC-Readout-Board
Muli-purpose 128-channel
Requires 1 channel for timing
Based on the HPTDC ASIC developed at CERN
GSI (M. Traxler et al.)
The time readout board is a custom board that is used for time measurement.
It is based on the HPTDC ASIC developed at CERN.
It has 128 channels, but requires 1 of them for timing.
It also contains a FPGA for, a single chip computer with ethernet, a DC/DC converter and memory.

21. DC-DC converter Input: +48V Output: +5V,-5V&+3.3V
2xDATEL 5V (12A)modules.
100mVpp
POLA 3.3V
40mVpp
Extra filtering at the input and output: 25mVpp
The power supply provides all voltages required for the Daughterboard, which are +5, -5 and +3.3 modules.
The board is based on DC/DC converter modules:
2 Datel modules with 5V outpu together with a Pola 3.3V
The PCB which allocates the modules provides extra filtering at the input and output
GSI (M. Traxler et al.)

22. Beam results 1GeV C-C collisions
Full chain:
Detector+FEE+TRB
ToFThr=15mV
ToTThr=-20mV
<0.5W/channel
Crosstalk<1%
Jitter: 50ps
Output width vs charge correlation for gamma illumination using 60Co source
Beam results 1GeV C-C collisions

23. Charge comparator removed
IMPROVEMENTS
DAUGHTERBOARD
Only one comparator
30% less consumption per channel
Expected to improve the output width vs. charge correlation
Charge comparator removed

24. IMPROVEMENTS MOTHERBOARD Ripple filtering improvement
DACs readback to check that the data has correctly received
Trigger system will be redesigned because the actual OPAMs produce big overshootlower slow rate

25. SUMMARY The actual FEE fits HADES requirements.
2 Motherboards with 64 channels has been evaluated under:
- pulse generator
- gamma source
- under beam
Still some improvements commented have to be done, as well as some long term stability tests. Noise/crosstalk measurements should be done in more detail.
Next step will be to cover 2 sectors of the actual detector in February 2007

26. Acknowledgments Hector Alvarez (LabCAF-Universidad de S. Compostela)
Alberto Blanco (LIP-Coimbra)
Paulo Fonte (LIP-Coimbra)
Gerhard May (GSI)
Martin Zapata (LabCAF-Universidad de S. Compostela)

27. Thanks for your attention