1. Datapath and Control AddressInstruction Memory Write Data Reg Addr Register File ALU Data Memory Address Write Data Read Data PC Read Data Read Data

2. u The control architecture can be treated as a Moore State Machine, with output depending only on the current state. States change at every clock cycle. u Instructions need different number of cycles (3-5) depending on the number of steps they have. u Some steps are common for all instructions. u Example - Instruction Fetch step u Also common is Instruction Decode and Register Fetch step u R-type Instruction Execution, Memory Read/Write Address Computation, Branch Completion, or Jump Completion are different u Memory Read Access, Memory Write Completion or R- type Instruction Completion u Memory Read Completion (Write Back) Five Instruction Steps

3.  Use PC to get instruction from the memory and put it in the Instruction Register MemoryRead =1, IRWrite =1,  Increment the PC by 4 and put the result back in the PC IorD =0 (to select PC), ALUSrcA =0, ALUSrcB =01, ALUOp =00 (add), PCWrite =1  Can be described succinctly using RTL "Register- Transfer Language“ IR = Memory[PC]; PC = PC + 4; Step 1: Instruction Fetch

4. Datapath Activity During Instruction Fetch Address Read Data (Instr. or Data) Memory PC Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU Write Data IR MDR A B ALUout Sign Extend Shift left 2 ALU control Shift left 2 ALUOp Control IRWrite MemtoReg MemWrite MemRead IorD PCWrite PCWriteCond RegDst RegWrite ALUSrcA ALUSrcB zero PCSource 1 1 1 1 1 1 0 0 0 0 0 0 2 2 3 4 Instr[5-0] Instr[25-0] PC[31-28] Instr[15-0] Instr[31-26] 32 28

5. Fetch Control Signals Settings Start Instr Fetch IorD=0 MemRead;IRWrite ALUSrcA=0 ALUsrcB=01 PCSource,ALUOp=00 PCWrite State 0

6. u Don’t know what the instruction is yet, so can only –Read registers rs and rt in case we need them –Compute the branch address in case the instruction is a branch ALUSrcB =11, ALUOp =00 (add), ALUSrcA =0 (select PC)  RTL: A = Reg[IR[25-21]]; B = Reg[IR[20-16]]; ALUOut = PC +(sign-extend(IR[15-0])<< 2); u We aren't setting any control lines based on the instruction (since we are busy "decoding" it in our control logic) Step 2: Instruction Decode and Register Fetch

7. Datapath Activity During Instruction Decode Address Read Data (Instr. or Data) Memory PC Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU Write Data IR MDR A B ALUout Sign Extend Shift left 2 ALU control Shift left 2 ALUOp Control IRWrite MemtoReg MemWrite MemRead IorD PCWrite PCWriteCond RegDst RegWrite ALUSrcA ALUSrcB zero PCSource 1 1 1 1 1 1 0 0 0 0 0 0 2 2 3 4 Instr[5-0] Instr[25-0] PC[31-28] Instr[15-0] Instr[31-26] 32 28

8. Decode Control Signals Settings Unless otherwise assigned PCWrite,IRWrite, MemWrite,RegWrite=0 others=X Start IorD=0 MemRead;IRWrite ALUSrcA=0 ALUsrcB=01 PCSource,ALUOp=00 PCWrite Instr Fetch Decode ALUSrcA=0 ALUsrcB=11 ALUOp=00

9. u ALU is performing one of four functions, based on instruction type  Memory reference ( lw and sw ): ALUop =00, ALUSrcB =10, ALUSrcA =1 ALUOut = A + sign-extend(IR[15-0]); u R-type: ALUop =10 (use function field), ALUSrcA =1, ALUScrB =00 ALUOut = A op B; Step 3 (instruction dependent)

10. u Branch: ALUSrcB =00, ALUSrcA =1, ALUop =01 (force subtraction), PCSource =01 (use ALUout), PCwritecond =1 (in case zero=1) if (A==B) PC = ALUOut; u Jump: PCWrite =1, PCsource =10 PC = PC[31-28] || (IR[25-0] << 2); Step 3 (instruction dependent)

11. Datapath Activity During Instruction Execute Address Read Data (Instr. or Data) Memory PC Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU Write Data IR MDR A B ALUout Sign Extend Shift left 2 ALU control Shift left 2 ALUOp Control IRWrite MemtoReg MemWrite MemRead IorD PCWrite PCWriteCond RegDst RegWrite ALUSrcA ALUSrcB zero PCSource 1 1 1 1 1 1 0 0 0 0 0 0 2 2 3 4 Instr[5-0] Instr[25-0] PC[31-28] Instr[15-0] Instr[31-26] 32 28

12. Execute Control Signals Settings Execute Start Instr Fetch Decode Unless otherwise assigned PCWrite,IRWrite, MemWrite,RegWrite=0 others=X ALUSrcA=0 ALUSrcB=11 ALUOp=00 PCWriteCond=0 IorD=0 MemRead;IRWrite ALUSrcA=0 ALUsrcB=01 PCSource,ALUOp=00 PCWrite (Op = lw or sw) ALUSrcA=1 ALUSrcB=10 ALUOp=00 PCWriteCond=0 (Op = R-type) ALUSrcA=1 ALUSrcB=00 ALUOp=10 PCWriteCond=0 (Op = beq) ALUSrcA=1 ALUSrcB=00 ALUOp=01 PCSource=01 PCWriteCond (Op = j) PCSource=10 PCWrite

13. u Memory reference: MemoryRead=1, IorD=1 MDR = Memory[ALUOut]; -- lw or MemoryWrite=1, IorD=1 Memory[ALUOut] = B; -- sw u R-type instruction completion RegDst=1, RegWrite=1, MemtoReg=0 Reg[IR[15-11]] = ALUOut; u Remember, the register write actually takes place at the end of the cycle on the clock edge Step 4 (instruction dependent)

14. Datapath Activity During Memory Access Address Read Data (Instr. or Data) Memory PC Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU Write Data IR MDR A B ALUout Sign Extend Shift left 2 ALU control Shift left 2 ALUOp Control IRWrite MemtoReg MemWrite MemRead IorD PCWrite PCWriteCond RegDst RegWrite ALUSrcA ALUSrcB zero PCSource 1 1 1 1 1 1 0 0 0 0 0 0 2 2 3 4 Instr[5-0] Instr[25-0] PC[31-28] Instr[15-0] Instr[31-26] 32 28

15. Memory Access Control Signals Settings Start Instr Fetch Decode Memory Access Execute (Op = R-type) (Op = beq) (Op = lw or sw) (Op = j) (Op = lw) (Op = sw) Unless otherwise assigned PCWrite,IRWrite, MemWrite,RegWrite=0 others=X IorD=0 MemRead;IRWrite ALUSrcA=0 ALUsrcB=01 PCSource,ALUOp=00 PCWrite ALUSrcA=0 ALUSrcB=11 ALUOp=00 PCWriteCond=0 ALUSrcA=1 ALUSrcB=10 ALUOp=00 PCWriteCond=0 ALUSrcA=1 ALUSrcB=00 ALUOp=10 PCWriteCond=0 ALUSrcA=1 ALUSrcB=00 ALUOp=01 PCSource=01 PCWriteCond PCSource=10 PCWrite RegDst=1 RegWrite MemtoReg=0 PCWriteCond=0 MemWrite IorD=1 PCWriteCond=0 MemRead IorD=1 PCWriteCond=0

16.  All we have left is the write back into the register file the data just read from memory for lw instruction RegDst =0, RegWrite =1, MemtoReg =1 Reg[IR[20-16]]= MDR; Step 5: Memory Read Completion (Write Back)

17. Datapath Activity During Write Back Address Read Data (Instr. or Data) Memory PC Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU Write Data IR MDR A B ALUout Sign Extend Shift left 2 ALU control Shift left 2 ALUOp Control IRWrite MemtoReg MemWrite MemRead IorD PCWrite PCWriteCond RegDst RegWrite ALUSrcA ALUSrcB zero PCSource 1 1 1 1 1 1 0 0 0 0 0 0 2 2 3 4 Instr[5-0] Instr[25-0] PC[31-28] Instr[15-0] Instr[31-26] 32 28

18. Write Back Control Signals Settings Start Instr Fetch Decode RegDst=0 RegWrite MemtoReg=1 Write Back Memory Access Execute (Op = R-type) (Op = beq) (Op = lw or sw) (Op = j) (Op = lw) (Op = sw) Unless otherwise assigned PCWrite,IRWrite, MemWrite,RegWrite=0 others=X IorD=0 MemRead;IRWrite ALUSrcA=0 ALUsrcB=01 PCSource,ALUOp=00 PCWrite ALUSrcA=0 ALUSrcB=11 ALUOp=00 PCWriteCond=0 ALUSrcA=1 ALUSrcB=10 ALUOp=00 PCWriteCond=0 ALUSrcA=1 ALUSrcB=00 ALUOp=10 PCWriteCond=0 ALUSrcA=1 ALUSrcB=00 ALUOp=01 PCSource=01 PCWriteCond PCSource=10 PCWrite RegDst=1 RegWrite MemtoReg=0 PCWriteCond=0 MemWrite IorD=1 PCWriteCond=0 MemRead IorD=1 PCWriteCond=0

19. StepR-typeMem RefBranchJump Instr fetch IR = Memory[PC]; PC = PC + 4; Decode A = Reg[IR[25-21]]; B = Reg[IR[20-16]]; ALUOut = PC +(sign-extend(IR[15-0])<< 2); Execute ALUOut = A op B; ALUOut = A + sign- extend (IR[15- 0]); if (A==B) PC = ALUOut; PC = PC[31-28] ||(IR[25- 0] << 2); Memory access Reg[IR[ 15-11]] = ALUOut; MDR = Memory[ALUOut] ; or Memory[ALUOut] = B; Write-back Reg[IR[20-16]] = MDR; RTL Summary

20.  Add addi to the classes of instructions supported - what influence on number of states of the machine? Instruction fetch and Instruction decode states are unchanged. ALUout = A+ sign-exte.(IR[15-0]) Completion Reg(IR[20-16])=ALUout Exercise 5.15 Instr Fetch IorD=0 MemRead;IRWrite ALUSrcA=0 ALUsrcB=01 PCSource,ALUOp=00 PCWrite Op = addi RegDst=0 RegWrite=1 ALUOp=00 MemtoReg=0 State 12 State 0 Decode ALUSrcA=0 ALUSrcB=11 ALUOp=00 PCWriteCond=0 State 1

21. Exercise 5.15 - Cont.  The finite state machine with the addition of the state to handle addi RegDst=0 RegWrite=1 ALUOp=00 MemtoReg=0 State 12 OP : addi

22. u Multi-cycle datapath control signals are not determined solely by the bits in the instruction –e.g., op code bits tell what operation the ALU should be doing, but not what instruction cycle is to be done next u We’ll use a finite state machine for control –a set of states (current state stored in State Register) –next state function (determined by current state and the input) –output function (determined by current state and the input) Multi-cycle Control

23. Combinational control logic Finite State Machine Implementation Next State State Reg Inputs Outputs Inst[31-26] Op0Op1Op2Op3Op4Op5 PCWrite PCWriteCond IorD MemRead MemWrite IRWrite MemtoReg PCSource ALUOp ALUSourceB ALUSourceA RegWrite RegDst System Clock u We’ll use a Moore machine (control signals based only on current state)

24. Datapath Control Outputs Truth Table OutputsInput Values (Current State[3-0]) 0000000100100011010001010110011110001001 PCWrite1000000001 PCWriteCondX00000001X IorD0XX1X1XXXX MemRead1XX1XXXXXX MemWrite0000010000 IRWrite1000000000 MemtoRegXXXX1XX0XX PCSource00XX 0110 ALUOp00 XX 10XX01XX ALUSrcB011110XX 00XX00XX ALUSrcA001XXX1X1X RegWrite0000100100 RegDstXXXX0XX1XX

25. Current State [3-0] Inst[31-26] (Op[5-0]) 000000 (R-type) 000010 (jmp) 000100 (beq) 100011 (lw) 101011 (sw) Any other 00000001 0110100110000010 illegal 0010XXXX 00110101illegal 0011XXXX 0100XXXXillegal 0100XXXX 0000XXXXillegal 0101XXXX 0000illegal 01100111XXXX illegal 01110000XXXX illegal 1000XXXX 0000XXXX illegal 1001XXXX0000XXXX illegal Next State Truth Table