1. CSE331 W10&11.1Irwin Fall 2007 PSU CSE 331 Computer Organization and Design Fall 2007 Week 10 & 11 Section 1: Mary Jane Irwin (www.cse.psu.edu/~mji)www.cse.psu.edu/~mji Section 2: Krishna Narayanan Course material on ANGEL: cms.psu.edu [ adapted from D. Patterson slides ]

2. CSE331 W10&11.2Irwin Fall 2007 PSU Head’s Up  Last week’s material l Designing a MIPS single cycle datapath  This week’s material and next week’s l More on single cycle datapath design and exam review -Reading assignment – PH: 5.4, B.8, C.1-C.2 l Multicycle MIPS datapath implementation -Reading assignment – PH: 5.5, B.10  The week after Exam #2 material l Finish multicycle MIPS datapath and control path implementation -Reading assignment – PH: 5.7, B.10, C.3-C.5  Reminders l Exam #1 take home solution due Thursday, Nov 1 st (by 11:55pm) l HW 7 is due Tuesday, Nov 27 th (by 11:55pm) l Quiz 6 closes Tuesday, Nov 5 th (by 11:55pm) l Exam #2 is Thursday, Nov 8 th, 6:30 to 7:45pm -People with conflicts should have sent email by now l Friday, Nov 16 th is the late-drop deadline l Final Exam is Tuesday, Dec 18 th, 10:10 to noon, 112 Walker

3. CSE331 W10&11.3Irwin Fall 2007 PSU Each MAS (microarchitectural specifications) included  Pipeline and block diagrams  Textual description of the theory of operation  Unit inputs and outputs and protocols governing data transfers  Corner cases of the design that were especially tricky  New circuits required for implementation  Notes on testing and validation The Pentium Chronicles, Colwell, pg. 82

4. CSE331 W10&11.4Irwin Fall 2007 PSU Review: Creating a Datapath from the Parts  Assemble the datapath elements, add control lines as needed, and design the control path  Fetch, decode and execute each instructions in one clock cycle – single cycle design l no datapath resource can be used more than once per instruction, so some must be duplicated (e.g., one reason why we have a separate Instruction Memory and Data Memory) l to share datapath elements between two different instruction classes need multiplexors at the input of the shared elements with control lines to do the selection  Cycle time is determined by length of the longest (slowest) path

5. CSE331 W10&11.5Irwin Fall 2007 PSU Review: A Simple MIPS Datapath Design Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU ovf zero ALU controlRegWrite Data Memory Address Write Data Read Data MemWrite MemRead Sign Extend 1632 MemtoReg ALUSrc Read Address Instruction Memory Add PC 4 Shift left 2 Add PCSrc

6. CSE331 W10&11.6Irwin Fall 2007 PSU Adding the Control  Selecting the operations to perform (ALU, Register File and Memory read/write)  Controlling the flow of data (multiplexor inputs)  Information comes from the 32 bits of the instruction I-Type: oprsrt address offset 312520150 R-type: 3125201550 oprsrtrdfunctshamt 10  Observations l op field always in bits 31-26 l addr of two registers to be read are always specified by the rs and rt fields (bits 25-21 and 20-16) l base register for lw and sw always in rs (bits 25-21) l addr. of register to be written is in one of two places – in rt (bits 20-16) for lw; in rd (bits 15-11) for R-type instructions l offset for beq, lw, and sw always in bits 15-0

7. CSE331 W10&11.7Irwin Fall 2007 PSU (Almost) Complete Single Cycle Datapath Read Address Instr[31-0] Instruction Memory Add PC 4 Write Data Read Addr 1 Read Addr 2 Write Addr ALU ovf zero Data Memory Address Write Data Read Data MemWrite MemRead Register File Read Data 1 Read Data 2 RegWrite Sign Extend 1632 MemtoReg ALUSrc Shift left 2 Add PCSrc 1 0 RegDst 0 1 1 0 1 0 ALU control ALUOp Instr[5-0] Instr[15-0] Instr[25-21] Instr[20-16] Instr[15 -11]

8. CSE331 W10&11.8Irwin Fall 2007 PSU ALU Control ALU control input Function 0000and 0001or 0010xor 0011nor 0110add 1110subtract 1111set on less than  ALU's operation based on instruction type and function code  Notice that we are using different encodings than in the book

9. CSE331 W10&11.9Irwin Fall 2007 PSU ALU Control, Con’t  Controlling the ALU uses of multiple decoding levels l main control unit generates the ALUOp bits l ALU control unit generates ALUcontrol bits Instr opfunctALUOpactionALUcontrol lwxxxxxx00 swxxxxxx00 beqxxxxxx01 add10000010add0110 subt10001010subtract1110 and10010010and0000 or10010110or0001 xor10011010xor0010 nor10011110nor0011 slt10101010slt1111

10. CSE331 W10&11.10Irwin Fall 2007 PSU ALU Control, Con’t  Controlling the ALU uses of multiple decoding levels l main control unit generates the ALUOp bits l ALU control unit generates ALUcontrol bits Instr opfunctALUOpactionALUcontrol lwxxxxxx00 swxxxxxx00 beqxxxxxx01 add10000010add0110 subt10001010subtract1110 and10010010and0000 or10010110or0001 xor10011010xor0010 nor10011110nor0011 slt10101010slt1111 add0110 add0110 subtract1110

11. CSE331 W10&11.11Irwin Fall 2007 PSU ALU Control Truth Table F5F4F3F2F1F0ALU Op 1 ALU Op 0 ALU control 3 ALU control 2 ALU control 1 ALU control 0 XXXXXX000110 XXXXXX011110 XX0000100110 XX0010101110 XX0100100000 XX0101100001 XX0110100010 XX0111100011 XX1010101111  Four, 6-input truth tables

12. CSE331 W10&11.12Irwin Fall 2007 PSU ALU Control Truth Table F5F4F3F2F1F0ALU Op 1 ALU Op 0 ALU control 3 ALU control 2 ALU control 1 ALU control 0 XXXXXX000110 XXXXXX011110 XX0000100110 XX0010101110 XX0100100000 XX0101100001 XX0110100010 XX0111100011 XX1010101111  Four, 6-input truth tables Our ALU m control input Add/subtMux control

13. CSE331 W10&11.13Irwin Fall 2007 PSU ALU Control Logic  From the truth table can design the ALU Control logic Instr[3] Instr[2] Instr[1] Instr[0] ALUOp 1 ALUOp 0 ALUcontrol 3 ALUcontrol 2 ALUcontrol 1 ALUcontrol 0

14. CSE331 W10&11.14Irwin Fall 2007 PSU (Almost) Complete Datapath with Control Unit Read Address Instr[31-0] Instruction Memory Add PC 4 Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU ovf zero RegWrite Data Memory Address Write Data Read Data MemWrite MemRead Sign Extend 1632 MemtoReg ALUSrc Shift left 2 Add PCSrc RegDst ALU control 1 1 1 0 0 0 0 1 ALUOp Instr[5-0] Instr[15-0] Instr[25-21] Instr[20-16] Instr[15 -11] Control Unit Instr[31-26] Branch

15. CSE331 W10&11.15Irwin Fall 2007 PSU Main Control Unit InstrRegDstALUSrcMemRegRegWrMemRdMemWrBranchALUOp R- type 000000 lw 100011 sw 101011 beq 000100  Completely determined by the instruction opcode field l Note that a multiplexor whose control input is 0 has a definite action, even if it is not used in performing the operation

16. CSE331 W10&11.16Irwin Fall 2007 PSU R-type Instruction Data/Control Flow Read Address Instr[31-0] Instruction Memory Add PC 4 Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU ovf RegWrite Data Memory Address Write Data Read Data MemWrite MemRead Sign Extend 1632 MemtoReg ALUSrc Shift left 2 Add PCSrc RegDst ALU control 1 1 1 0 0 0 0 1 ALUOp Instr[5-0] Instr[15-0] Instr[25-21] Instr[20-16] Instr[15 -11] Control Unit Instr[31-26] Branch zero

17. CSE331 W10&11.17Irwin Fall 2007 PSU R-type Instruction Data/Control Flow Read Address Instr[31-0] Instruction Memory Add PC 4 Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU ovf zero RegWrite Data Memory Address Write Data Read Data MemWrite MemRead Sign Extend 1632 MemtoReg ALUSrc Shift left 2 Add PCSrc RegDst ALU control 1 1 1 0 0 0 0 1 ALUOp Instr[5-0] Instr[15-0] Instr[25-21] Instr[20-16] Instr[15 -11] Control Unit Instr[31-26] Branch

18. CSE331 W10&11.18Irwin Fall 2007 PSU Store Word Instruction Data/Control Flow Read Address Instr[31-0] Instruction Memory Add PC 4 Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU ovf zero RegWrite Data Memory Address Write Data Read Data MemWrite MemRead Sign Extend 1632 MemtoReg ALUSrc Shift left 2 Add PCSrc RegDst ALU control 1 1 1 0 0 0 0 1 ALUOp Instr[5-0] Instr[15-0] Instr[25-21] Instr[20-16] Instr[15 -11] Control Unit Instr[31-26] Branch

19. CSE331 W10&11.19Irwin Fall 2007 PSU Store Word Instruction Data/Control Flow Read Address Instr[31-0] Instruction Memory Add PC 4 Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU ovf zero RegWrite Data Memory Address Write Data Read Data MemWrite MemRead Sign Extend 1632 MemtoReg ALUSrc Shift left 2 Add PCSrc RegDst ALU control 1 1 1 0 0 0 0 1 ALUOp Instr[5-0] Instr[15-0] Instr[25-21] Instr[20-16] Instr[15 -11] Control Unit Instr[31-26] Branch

20. CSE331 W10&11.20Irwin Fall 2007 PSU Load Word Instruction Data/Control Flow Read Address Instr[31-0] Instruction Memory Add PC 4 Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU ovf zero RegWrite Data Memory Address Write Data Read Data MemWrite MemRead Sign Extend 1632 MemtoReg ALUSrc Shift left 2 Add PCSrc RegDst ALU control 1 1 1 0 0 0 0 1 ALUOp Instr[5-0] Instr[15-0] Instr[25-21] Instr[20-16] Instr[15 -11] Control Unit Instr[31-26] Branch

21. CSE331 W10&11.21Irwin Fall 2007 PSU Load Word Instruction Data/Control Flow Read Address Instr[31-0] Instruction Memory Add PC 4 Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU ovf zero RegWrite Data Memory Address Write Data Read Data MemWrite MemRead Sign Extend 1632 MemtoReg ALUSrc Shift left 2 Add PCSrc RegDst ALU control 1 1 1 0 0 0 0 1 ALUOp Instr[5-0] Instr[15-0] Instr[25-21] Instr[20-16] Instr[15 -11] Control Unit Instr[31-26] Branch

22. CSE331 W10&11.22Irwin Fall 2007 PSU Branch Instruction Data/Control Flow Read Address Instr[31-0] Instruction Memory Add PC 4 Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU ovf zero RegWrite Data Memory Address Write Data Read Data MemWrite MemRead Sign Extend 1632 MemtoReg ALUSrc Shift left 2 Add PCSrc RegDst ALU control 1 1 1 0 0 0 0 1 ALUOp Instr[5-0] Instr[15-0] Instr[25-21] Instr[20-16] Instr[15 -11] Control Unit Instr[31-26] Branch

23. CSE331 W10&11.23Irwin Fall 2007 PSU Branch Instruction Data/Control Flow Read Address Instr[31-0] Instruction Memory Add PC 4 Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU ovf zero RegWrite Data Memory Address Write Data Read Data MemWrite MemRead Sign Extend 1632 MemtoReg ALUSrc Shift left 2 Add PCSrc RegDst ALU control 1 1 1 0 0 0 0 1 ALUOp Instr[5-0] Instr[15-0] Instr[25-21] Instr[20-16] Instr[15 -11] Control Unit Instr[31-26] Branch

24. CSE331 W10&11.24Irwin Fall 2007 PSU Main Control Unit InstrRegDstALUSrcMemRegRegWrMemRdMemWrBranchALUOp R-type 000000 100100010 lw 100011 011110000 sw 101011 X1X001000 beq 000100 X0X000101  Setting of the MemRd signal (for R-type, sw, beq) depends on the memory design (could have to be 0 or could be a X (don’t care))

25. CSE331 W10&11.25Irwin Fall 2007 PSU Control Unit Logic  From the truth table can design the Main Control logic Instr[31] Instr[30] Instr[29] Instr[28] Instr[27] Instr[26] R-type lwswbeq RegDst ALUSrc MemtoReg RegWrite MemRead MemWrite Branch ALUOp 1 ALUOp 0

26. CSE331 W10&11.26Irwin Fall 2007 PSU Review: Handling Jump Operations  Jump operation have to l replace the lower 28 bits of the PC with the lower 26 bits of the fetched instruction shifted left by 2 bits Read Address Instruction Memory Add PC 4 Shift left 2 Jump address 26 4 28 J-Type: opjump target address 310

27. CSE331 W10&11.27Irwin Fall 2007 PSU Adding the Jump Operation Read Address Instr[31-0] Instruction Memory Add PC 4 Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU ovf zero RegWrite Data Memory Address Write Data Read Data MemWrite MemRead Sign Extend 1632 MemtoReg ALUSrc Shift left 2 Add PCSrc RegDst ALU control 1 1 1 0 0 0 0 1 ALUOp Instr[5-0] Instr[15-0] Instr[25-21] Instr[20-16] Instr[15 -11] Control Unit Instr[31-26] Branch Shift left 2 0 1 Jump 32 Instr[25-0] 26 PC+4[31-28] 28

28. CSE331 W10&11.28Irwin Fall 2007 PSU Adding the Jump Operation Read Address Instr[31-0] Instruction Memory Add PC 4 Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU ovf zero RegWrite Data Memory Address Write Data Read Data MemWrite MemRead Sign Extend 1632 MemtoReg ALUSrc Shift left 2 Add PCSrc RegDst ALU control 1 1 1 0 0 0 0 1 ALUOp Instr[5-0] Instr[15-0] Instr[25-21] Instr[20-16] Instr[15 -11] Control Unit Instr[31-26] Branch Shift left 2 0 1 Jump 32 Instr[25-0] 26 PC+4[31-28] 28

29. CSE331 W10&11.29Irwin Fall 2007 PSU Main Control Unit InstrRegDstALUSrcMemRegRegWrMemRdMemWrBranchALUOpJump R-type 000000 lw 100011 sw 101011 beq 000100 j 000010  Setting of the MemRd signal (for R-type, sw, beq) depends on the memory design

30. CSE331 W10&11.30Irwin Fall 2007 PSU Main Control Unit InstrRegDstALUSrcMemRegRegWrMemRdMemWrBranchALUOpJump R-type 000000 1001000100 lw 100011 0111100000 sw 101011 X1X0010000 beq 000100 X0X0001010 j 000010 XXX000XXX1  Setting of the MemRd signal (for R-type, sw, beq) depends on the memory design

31. CSE331 W10&11.31Irwin Fall 2007 PSU End of First Lecture of the Week

32. CSE331 W10&11.32Irwin Fall 2007 PSU  Need another Colwell quote or Dilbert here

33. CSE331 W10&11.33Irwin Fall 2007 PSU Single Cycle Implementation Cycle Time  Unfortunately, though simple, the single cycle approach is not used because it is very slow  Clock cycle must have the same length for every instruction  What is the longest (slowest) path (slowest instruction)?

34. CSE331 W10&11.34Irwin Fall 2007 PSU Instruction Critical Paths Instr.I MemReg RdALU OpD MemReg WrTotal R- type load store beq jump  Calculate cycle time assuming negligible delays (for muxes, control unit, sign extend, PC access, shift left 2, wires) except: l Instruction and Data Memory (4 ns) l ALU and adders (2 ns) l Register File access (reads or writes) (1 ns)

35. CSE331 W10&11.35Irwin Fall 2007 PSU Instruction Critical Paths Instr.I MemReg RdALU OpD MemReg WrTotal R- type load store beq jump 41218 4124112  Calculate cycle time assuming negligible delays (for muxes, control unit, sign extend, PC access, shift left 2, wires, setup and hold times) except: l Instruction and Data Memory (4 ns) l ALU and adders (2 ns) l Register File access (reads or writes) (1 ns) 412411 4127 44

36. CSE331 W10&11.36Irwin Fall 2007 PSU Single Cycle Disadvantages & Advantages  Uses the clock cycle inefficiently – the clock cycle must be timed to accommodate the slowest instr l especially problematic for more complex instructions like floating point multiply  May be wasteful of area since some functional units (e.g., adders) must be duplicated since they can not be shared during a clock cycle but  It is simple and easy to understand Clk lwswWaste Cycle 1Cycle 2

37. CSE331 W10&11.37Irwin Fall 2007 PSU Multicycle Implementation Overview  Each instruction step takes 1 clock cycle l Therefore, an instruction takes more than 1 clock cycle to complete  Not every instruction takes the same number of clock cycles to complete  Multicycle implementations allow l faster clock rates l different instructions to take a different number of clock cycles l functional units to be used more than once per instruction as long as they are used on different clock cycles, as a result -only need one memory -only need one ALU/adder

38. CSE331 W10&11.38Irwin Fall 2007 PSU The Multicycle Datapath – A High Level View Address Read Data (Instr. or Data) Memory PC Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU Write Data IR MDR A B ALUout  Registers have to be added after every major functional unit to hold the output value until it is used in a subsequent clock cycle

39. CSE331 W10&11.39Irwin Fall 2007 PSU Clocking the Multicycle Datapath Address Read Data (Instr. or Data) Memory PC Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU Write Data IR MDR A B ALUout System Clock MemWriteRegWrite clock cycle

40. CSE331 W10&11.40Irwin Fall 2007 PSU  Break up the instructions into steps where each step takes a clock cycle while trying to l balance the amount of work to be done in each step l use only one major functional unit per clock cycle  At the end of a clock cycle l Store values needed in a later clock cycle by the current instruction in a state element (internal register not visible to the programmer) IR – Instruction Register MDR – Memory Data Register A and B – Register File read data registers ALUout – ALU output register -All (except IR) hold data only between a pair of adjacent clock cycles (so they don’t need a write control signal) l Data used by subsequent instructions are stored in programmer visible state elements (i.e., Register File, PC, or Memory) Our Multicycle Approach

41. CSE331 W10&11.41Irwin Fall 2007 PSU The Complete Multicycle Data with Control Address Read Data (Instr. or Data) Memory PC Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU Write Data IR MDR A B ALUout Sign Extend Shift left 2 ALU control Shift left 2 ALUOp Control IRWrite MemtoReg MemWrite MemRead IorD PCWrite PCWriteCond RegDst RegWrite ALUSrcA ALUSrcB zero PCSource 1 1 1 1 1 1 0 0 0 0 0 0 2 2 3 4 Instr[5-0] Instr[25-0] PC[31-28] Instr[15-0] Instr[31-26] 32 28

42. CSE331 W10&11.42Irwin Fall 2007 PSU Review: Our ALU Control  Controlling the ALU uses of multiple decoding levels l main control unit generates the ALUOp bits l ALU control unit generates ALUcontrol bits Instr opfunctALUOpactionALUcontrol lwxxxxxx00add0110 swxxxxxx00add0110 beqxxxxxx01subtract1110 add10000010add0110 subt10001010subtract1110 and10010010and0000 or10010110or0001 xor10011010xor0010 nor10011110nor0011 slt10101010slt1111

43. CSE331 W10&11.43Irwin Fall 2007 PSU  Reading from or writing to any of the internal registers, Register File, or the PC occurs (quickly) at the beginning (for read) or the end of a clock cycle (for write)  Reading from the Register File takes ~50% of a clock cycle since it has additional control and access overhead (but reading can be done in parallel with decode)  Had to add multiplexors in front of several of the functional unit input ports (e.g., Memory, ALU) because they are now shared by different clock cycles and/or do multiple jobs  All operations occurring in one clock cycle occur in parallel l This limits us to one ALU operation, one Memory access, and one Register File access per clock cycle Our Multicycle Approach, con’t

44. CSE331 W10&11.44Irwin Fall 2007 PSU 1. Instruction Fetch 2. Instruction Decode and Register Fetch 3. R-type Instruction Execution, Memory Read/Write Address Computation, Branch Completion, or Jump Completion 4. Memory Read Access, Memory Write Completion or R-type Instruction Completion 5. Memory Read Completion (Write Back) INSTRUCTIONS TAKE FROM 3 - 5 CYCLES! Five Instruction Steps

45. CSE331 W10&11.45Irwin Fall 2007 PSU  Use PC to get instruction from the memory and put it in the Instruction Register  Increment the PC by 4 and put the result back in the PC  Can be described succinctly using the RTL "Register- Transfer Language“ IR = Memory[PC]; PC = PC + 4; Step 1: Instruction Fetch Can we figure out the values of the control signals? What is the advantage of updating the PC now?

46. CSE331 W10&11.46Irwin Fall 2007 PSU Datapath Activity During Instruction Fetch Address Read Data (Instr. or Data) Memory PC Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU Write Data IR MDR A B ALUout Sign Extend Shift left 2 ALU control Shift left 2 ALUOp Control IRWrite MemtoReg MemWrite MemRead IorD PCWrite PCWriteCond RegDst RegWrite ALUSrcA ALUSrcB zero PCSource 1 1 1 1 1 1 0 0 0 0 0 0 2 2 3 4 Instr[5-0] Instr[25-0] PC[31-28] Instr[15-0] Instr[31-26] 32 28

47. CSE331 W10&11.47Irwin Fall 2007 PSU Datapath Activity During Instruction Fetch Address Read Data (Instr. or Data) Memory PC Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU Write Data IR MDR A B ALUout Sign Extend Shift left 2 ALU control Shift left 2 ALUOp Control IRWrite MemtoReg MemWrite MemRead IorD PCWrite PCWriteCond RegDst RegWrite ALUSrcA ALUSrcB zero PCSource 1 1 1 1 1 1 0 0 0 0 0 0 2 2 3 4 Instr[5-0] Instr[25-0] PC[31-28] Instr[15-0] Instr[31-26] 32 28 00

48. CSE331 W10&11.48Irwin Fall 2007 PSU Fetch Control Signals Settings Start Instr Fetch

49. CSE331 W10&11.49Irwin Fall 2007 PSU Fetch Control Signals Settings Start Instr Fetch IorD=0 MemRead;IRWrite ALUSrcA=0 ALUsrcB=01 PCSource,ALUOp=00 PCWrite Unless otherwise assigned PCWrite,IRWrite, MemWrite,RegWrite=0 others=X

50. CSE331 W10&11.50Irwin Fall 2007 PSU  Don’t know what the instruction is yet, so can only l Read registers rs and rt in case we need them l Compute the branch address in case the instruction is a branch  The RTL: A = Reg[IR[25-21]]; B = Reg[IR[20-16]]; ALUOut = PC +(sign-extend(IR[15-0])<< 2);  Note we aren't setting any control lines based on the instruction (since we don’t know what it is (the control logic is busy "decoding" the op code bits)) Step 2: Instruction Decode and Register Fetch

51. CSE331 W10&11.51Irwin Fall 2007 PSU Datapath Activity During Instruction Decode Address Read Data (Instr. or Data) Memory PC Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU Write Data IR MDR A B ALUout Sign Extend Shift left 2 ALU control Shift left 2 ALUOp Control IRWrite MemtoReg MemWrite MemRead IorD PCWrite PCWriteCond RegDst RegWrite ALUSrcA ALUSrcB zero PCSource 1 1 1 1 1 1 0 0 0 0 0 0 2 2 3 4 Instr[5-0] Instr[25-0] PC[31-28] Instr[15-0] Instr[31-26] 32 28

52. CSE331 W10&11.52Irwin Fall 2007 PSU Datapath Activity During Instruction Decode Address Read Data (Instr. or Data) Memory PC Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU Write Data IR MDR A B ALUout Sign Extend Shift left 2 ALU control Shift left 2 ALUOp Control IRWrite MemtoReg MemWrite MemRead IorD PCWrite PCWriteCond RegDst RegWrite ALUSrcA ALUSrcB zero PCSource 1 1 1 1 1 1 0 0 0 0 0 0 2 2 3 4 Instr[5-0] Instr[25-0] PC[31-28] Instr[15-0] Instr[31-26] 32 28 00

53. CSE331 W10&11.53Irwin Fall 2007 PSU Decode Control Signals Settings Start Instr Fetch Decode Unless otherwise assigned PCWrite,IRWrite, MemWrite,RegWrite=0 others=X IorD=0 MemRead;IRWrite ALUSrcA=0 ALUsrcB=01 PCSource,ALUOp=00 PCWrite

54. CSE331 W10&11.54Irwin Fall 2007 PSU Decode Control Signals Settings Start Instr Fetch Decode ALUSrcA=0 ALUSrcB=11 ALUOp=00 PCWriteCond=0 IorD=0 MemRead;IRWrite ALUSrcA=0 ALUsrcB=01 PCSource,ALUOp=00 PCWrite Unless otherwise assigned PCWrite,IRWrite, MemWrite,RegWrite=0 others=X

55. CSE331 W10&11.55Irwin Fall 2007 PSU  ALU is performing one of four functions, based on instruction type  Memory reference ( lw and sw ): ALUOut = A + sign-extend(IR[15-0]);  R-type: ALUOut = A op B;  Branch: if (A==B) PC = ALUOut;  Jump: PC = PC[31-28] || (IR[25-0] << 2); Step 3 (instruction dependent)

56. CSE331 W10&11.56Irwin Fall 2007 PSU Datapath Activity During lw & sw Execute Address Read Data (Instr. or Data) Memory PC Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU Write Data IR MDR A B ALUout Sign Extend Shift left 2 ALU control Shift left 2 ALUOp Control IRWrite MemtoReg MemWrite MemRead IorD PCWrite PCWriteCond RegDst RegWrite ALUSrcA ALUSrcB zero PCSource 1 1 1 1 1 1 0 0 0 0 0 0 2 2 3 4 Instr[5-0] Instr[25-0] PC[31-28] Instr[15-0] Instr[31-26] 32 28

57. CSE331 W10&11.57Irwin Fall 2007 PSU Datapath Activity During lw & sw Execute Address Read Data (Instr. or Data) Memory PC Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU Write Data IR MDR A B ALUout Sign Extend Shift left 2 ALU control Shift left 2 ALUOp Control IRWrite MemtoReg MemWrite MemRead IorD PCWrite PCWriteCond RegDst RegWrite ALUSrcA ALUSrcB zero PCSource 1 1 1 1 1 1 0 0 0 0 0 0 2 2 3 4 Instr[5-0] Instr[25-0] PC[31-28] Instr[15-0] Instr[31-26] 32 28 00

58. CSE331 W10&11.58Irwin Fall 2007 PSU Datapath Activity During R-type Execute Address Read Data (Instr. or Data) Memory PC Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU Write Data IR MDR A B ALUout Sign Extend Shift left 2 ALU control Shift left 2 ALUOp Control IRWrite MemtoReg MemWrite MemRead IorD PCWrite PCWriteCond RegDst RegWrite ALUSrcA ALUSrcB zero PCSource 1 1 1 1 1 1 0 0 0 0 0 0 2 2 3 4 Instr[5-0] Instr[25-0] PC[31-28] Instr[15-0] Instr[31-26] 32 28

59. CSE331 W10&11.59Irwin Fall 2007 PSU Datapath Activity During R-type Execute Address Read Data (Instr. or Data) Memory PC Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU Write Data IR MDR A B ALUout Sign Extend Shift left 2 ALU control Shift left 2 ALUOp Control IRWrite MemtoReg MemWrite MemRead IorD PCWrite PCWriteCond RegDst RegWrite ALUSrcA ALUSrcB zero PCSource 1 1 1 1 1 1 0 0 0 0 0 0 2 2 3 4 Instr[5-0] Instr[25-0] PC[31-28] Instr[15-0] Instr[31-26] 32 28 10

60. CSE331 W10&11.60Irwin Fall 2007 PSU Datapath Activity During beq Execute Address Read Data (Instr. or Data) Memory PC Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU Write Data IR MDR A B ALUout Sign Extend Shift left 2 ALU control Shift left 2 ALUOp Control IRWrite MemtoReg MemWrite MemRead IorD PCWrite PCWriteCond RegDst RegWrite ALUSrcA ALUSrcB zero PCSource 1 1 1 1 1 1 0 0 0 0 0 0 2 2 3 4 Instr[5-0] Instr[25-0] PC[31-28] Instr[15-0] Instr[31-26] 32 28

61. CSE331 W10&11.61Irwin Fall 2007 PSU Datapath Activity During beq Execute Address Read Data (Instr. or Data) Memory PC Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU Write Data IR MDR A B ALUout Sign Extend Shift left 2 ALU control Shift left 2 ALUOp Control IRWrite MemtoReg MemWrite MemRead IorD PCWrite PCWriteCond RegDst RegWrite ALUSrcA ALUSrcB zero PCSource 1 1 1 1 1 1 0 0 0 0 0 0 2 2 3 4 Instr[5-0] Instr[25-0] PC[31-28] Instr[15-0] Instr[31-26] 32 28 01

62. CSE331 W10&11.62Irwin Fall 2007 PSU Datapath Activity During j Execute Address Read Data (Instr. or Data) Memory PC Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU Write Data IR MDR A B ALUout Sign Extend Shift left 2 ALU control Shift left 2 ALUOp Control IRWrite MemtoReg MemWrite MemRead IorD PCWrite PCWriteCond RegDst RegWrite ALUSrcA ALUSrcB zero PCSource 1 1 1 1 1 1 0 0 0 0 0 0 2 2 3 4 Instr[5-0] Instr[25-0] PC[31-28] Instr[15-0] Instr[31-26] 32 28

63. CSE331 W10&11.63Irwin Fall 2007 PSU Datapath Activity During j Execute Address Read Data (Instr. or Data) Memory PC Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU Write Data IR MDR A B ALUout Sign Extend Shift left 2 ALU control Shift left 2 ALUOp Control IRWrite MemtoReg MemWrite MemRead IorD PCWrite PCWriteCond RegDst RegWrite ALUSrcA ALUSrcB zero PCSource 1 1 1 1 1 1 0 0 0 0 0 0 2 2 3 4 Instr[5-0] Instr[25-0] PC[31-28] Instr[15-0] Instr[31-26] 32 28

64. CSE331 W10&11.64Irwin Fall 2007 PSU Execute Control Signals Settings Start Instr Fetch Decode Execute (Op = R-type) (Op = beq) (Op = lw or sw) (Op = j) Unless otherwise assigned PCWrite,IRWrite, MemWrite,RegWrite=0 others=X ALUSrcA=0 ALUSrcB=11 ALUOp=00 PCWriteCond=0 IorD=0 MemRead;IRWrite ALUSrcA=0 ALUsrcB=01 PCSource,ALUOp=00 PCWrite

65. CSE331 W10&11.65Irwin Fall 2007 PSU Execute Control Signals Settings Start Instr Fetch Decode (Op = R-type) (Op = beq) (Op = lw or sw) (Op = j) ALUSrcA=1 ALUSrcB=10 ALUOp=00 PCWriteCond=0 ALUSrcA=1 ALUSrcB=00 ALUOp=10 PCWriteCond=0 ALUSrcA=1 ALUSrcB=00 ALUOp=01 PCSource=01 PCWriteCond PCSource=10 PCWrite Execute Unless otherwise assigned PCWrite,IRWrite, MemWrite,RegWrite=0 others=X ALUSrcA=0 ALUSrcB=11 ALUOp=00 PCWriteCond=0 IorD=0 MemRead;IRWrite ALUSrcA=0 ALUsrcB=01 PCSource,ALUOp=00 PCWrite

66. CSE331 W10&11.66Irwin Fall 2007 PSU Where We are Headed After Exam #2  Finish the design of the multi-cycle machine l Step 4 and step 5 data path design l control path design for the multi-cycle machine l a microprogramming approach for control path design Address Read Data (Instr. or Data) Memory PC Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU Write Data IR MDR A B ALUout